Flip-Flop Delay Parameters SIMPLIS Flip-Flops

The example below shows an edge-triggered D-type Flip-Flop with asynchronous set and reset. In this example, set and reset are active high. The following diagram shows the definition of the clock-to-output delay as well as the set/reset delay. All Flip-Flop devices have a clock-to-output delay parameter, and all Flip-Flops with the set and reset feature have a set/reset delay.

Flip-Flop Minimum Clock Width

In the following example of a D-type Flip-Flop, the device is set to trigger on the positive-going edge of the clock and the clock pulse is ignored if the width of the clock pulse is narrower than the specified minimum clock width.