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In this Topic Hide
| Axxxx [ data_in_0 data_in_1 .. data_in_n ] [ data_out_0 data_out_1 .. |
| + data_out_n ] [ address_0 address_1 .. address_n ] write_en |
| + [ select_0 select_1 .. select_n ] model_name |
| Name | Description | Flow | Type | Vector bounds |
|---|---|---|---|---|
| data_in | Data input line(s) | in | d, vector | $1 - \infty$ |
| data_out | Data output line(s) | out | d, vector | $1 - \infty$ |
| address | Address input line(s) | in | d, vector | $1 - \infty$ |
| write_en | Write enable | in | d | n/a |
| select | Chip select line(s) | in | d, vector | 1 - 16 |
| .MODEL model_name d_ram parameters |
| Name | Description | Type | Default | Limits |
|---|---|---|---|---|
| select_value | Decimal active value for select line comparison | integer | 1 | 0 - 32767 |
| ic | Initial bit state @ DC | integer | 2 | 0 - 2 |
| read_delay | Read delay from address/select/write_en active | real | 1.00E-07 | $1\text{e}^{-12} - \infty$ |
| data_load | Data_in load value (F) | real | 1pF | none |
| address_load | Address line load value (F) | real | 1pF | none |
| select_load | Select load value (F) | real | 1pF | none |
| enable_load | Enable line load value (F) | real | 1pF | none |
This device is provided for compatibility with other XSPICE products and is not recommended for new designs. In some circumstances, this device can consume large quantities of system (i.e. your PC's) RAM as it uses an inefficient method of storing state history. RAM's can also be implemented using the arbitrary logic block (see Arbitrary Logic Block - User Defined Models) which is much more efficient. An example of a simple 256X8 RAM can be found amongst the supplied example circuits (Examples/ALB_Examples/RAM.sxsch and RAM.ldf).
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