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While that is our idealistic intention, reality never allows ideals. Verilog-A has quite a few little limitations that we would not want to impose on our users. Some of these we have already addressed and made non-standard extensions to do so. These are detailed below.
We will endeavour in the long run to make such extensions in a manner that would allow a source file to work with other Verilog-A simulators without modification.
According to the syntax specification, analog operators, e.g. ddt(), limexp(), white_noise(), may only be used in a standalone manner and may not be embedded in expressions. For example, this is allowed:
| V(n1, n2) <+ ddt(C*I(n1,n2)) ; |
but this isn't:
| V(n1, n2) <+ C*ddt(I(n1,n2)) ; |
But you would be allowed to do this:
| dd = ddt(I(n1,n2)) ; |
| V(n1, n2) <+ C * dd ; |
This limitation doesn't make any sense. It might make sense if any variable that an analog operator was assigned to was required to have a discipline defined. Then, the we could make sense of what tolerances to use for ddt() operations for example. But such a requirement is not present, indeed there is no method of assigning a discipline to a variable. So tolerance for ddt() is somewhat hit and miss anyway.
The later language reference manual version 2.3 does in fact not impose the above restrictions. It's possible that these restrictions are a consequence of errors in the definition in the language and not actually intentional.
Currently the $limit function remains subject to the above limitation. But we plan to change this in a future revision.
The Verlog-A language does not distinguish between instance parameters and model parameters. An instance parameter is one that can be defined on the device line on a per instance basis whereas a model parameter is one defined in a .MODEL statement. The most flexible implementation is one that allows both, with the instance parameter taking precedence if both are specified by the user. However this method has a cost in terms of increased memory usage per instance. While memory consumption may not seem to be a big issue, it can impact on performance. The less memory used, the more likely that the processor will find what it wants in the cache. For this reason it is desirable to minimise the number of instance parameters.
The SIMetrix Verilog-A implementation provides two methods of defining instance parameters: one in the verilog-A source file and the other on the command line of va.exe which in turn can be passed from .LOAD.
To define an instance parameter in the .VA file, prefix the parameter key word with the special attribute 'type' with a value of "instance". This is how it should look:
| (* type="instance" *) parameter a = 1 ; |
To define on .LOAD, add the parameter "instparams=parameter_list" where parameter_list is a comma separated list of parameter names.
If a parameter is defined as an instance parameter, it will also be available as a model parameter. If both are specified, the instance value will take precedence.
You may control how the new device is represented in SIMetrix using a device mapping. This does the same as the sxcfg file. Mappings are applied as a module attribute in the form:
( * Mappings="mapping_defs" * )
This should prefix the "module" keyword.
mapping_def is a semi-colon delimited list of mapping definitions. Each mapping definition is itself a comma delimited list of attibutes in the following order:
model-type-name,level-number,device-letter,default-parameter,version
Where:
| model-type-name | The name used in the .MODEL statement. |
| level | The LEVEL parameter value in the .MODEL statement. |
| device-letter | The device letter to use for this device. |
| default-parameter | A single parameter name and value. This is intended to be used to define device polarity. E.g. "pnp=1" might define a PNP BJT. This is useful to allow the definition of BJTs and MOS devices using conventional NPN/PNP or NMOS/PMOS model type names. |
| version | Value of VERSION parameter. |
For example, the HICUM device is defined with the following mapping:
(* Mappings="hicum_211,0;npn,8,Q,pnp=0,;pnp,8,Q,pnp=1," *)
This has three mappings. You can use hicum_211 with no level parameter to define a model. In this case the pnp parameter would need to be set for a PNP device. Alternatively you can use NPN as a model type name along with LEVEL=8 for an NPN device, or PNP with LEVEL=8 for a PNP device.
The Verilog-A language only allows for absoulte tolerances to be hardwired in the VA source file. This means for example, that absolute current tolerance, must be specified as a fixed constant which cannot be changed in the .OPTIONS line or anywhere else.
SIMetrix provides a workaround for this using the special values $abstol, $vntol, $chgtol and $fluxtol. These can be used to define absolute tolerances in electrical nature definitions. These are already used in the standard discipline header files supplied with the SIMetrix Verilog-A compiler.
Additional analyis types:
Standard types supported by SIMetrix:
Additional SIMetrix extensions:
"ptaScaleFactor" - as "sourceScaleFactor" but functional in pseudo transient analysis only. Default = 1.0.
In addition you can specify any option setting defined using .OPTIONS. E.g. $simparam("reltol") will return the value of the RELTOL option.
Use the argument "<listfile>" to write to the list file. This is the file created by every simulation with the extension .OUT.
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