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To implement a capacitor we need a time derivative function. In Verilog-A this is achieved using the ddt analog operator. A capacitor can be defined using the branch contribution statement:
| I(p,n) <+ capacitance * ddt( V(p,n)) ; |
Like the resistor, this defines the current/voltage relationship that the simulator must maintain on the nodes p and n. However, this definition has time dependence.
Here is the complete definition for a capacitor:
| `include "disciplines.vams" |
| module va_capacitor(p,n) ; |
| parameter real capacitance = 1n ; |
| electrical p, n ; |
| analog |
| I(p,n) <+ capacitance * ddt(V(p,n)) ; |
| endmodule |
See Examples/Manual/Capacitor. Note there is another definition for a capacitor with an initial condition parameter - capacitor_with_ic.va. This uses the time integration operator idt which allows the specification of an initial condition.
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