DVM Tutorial

8.1 Adding Power Losses to a Testplan

The built-in efficiency testplan measures the overall efficiency of the converter. In this section, you learn how to make the following additions to the built-in efficiency testplan:

• Add individual power losses to the report so you can observe how the power losses vary over line and load changes.
• Separate the gate-drive power loss from the input source power of the circuit.

This example generates five graphs:

• Total switching losses for the MOSFET in a sync buck circuit
• Total conduction losses for the MOSFET in a sync buck circuit
• Overall efficiency
• Gate-drive power loss
• Remaining losses in the circuit

  Note: To plot the remaining power losses, you will use a feature of the CreateXYScalarPlot() function to plot mathematical expressions of measured scalar values.

This example is based on a new schematic that uses discrete packaged MOSFETs that allow the MOSFET losses to be measured directly. The efficiency and power-loss schematic shown below is available from  SIMPLIS_dvm_tutorial_examples.zip at this path:
ISL6527A\8.1_Sync Buck Efficiency.sxsch

When compared with previous schematics, notice the following differences:

• Fixed power probes with the "mean" fixed probe measurement applied have been placed on the MOSFETs Q1 and Q2. These probes generate the scalar values for the total loss in the devices.
• A second input source has been added to supply power to the high-side gate driver. When DVM calculates the efficiency of a circuit, it includes the power from all input sources and all output loads. The individual power delivered by each input source and dissipated by each output load is also measured and reported as a scalar value.
• The names of the sources have been changed to be more descriptive of their function for the following reasons:
• The names for both probes and sources are important because the generated scalar names include those names.
• Since the testplan uses the Alias function to generate unique scalar names, the testplan and schematic must have the same probe, source, and load names. This is important to remember when taking an existing testplan and using it on a new schematic.

This prepared schematic runs exactly like the built-in efficiency testplan.

• The scalar values will be generated by the probes and by DVM.
• Those scalars are then assigned aliases based on the input voltage for the test.
• After all the tests complete, a final test is executed which generates the summary curves. Instead of using the create column to define the CreateXYScalarPlot() curve functions, a final-process script helps make the testplan more manageable. This script is available from  SIMPLIS_dvm_tutorial_examples.zip at this path:
  scripts/8.1_efficiency_and_powerloss_post_process.sxscr

The one portion of this script that needs discussing is the scalar expression capabilities of the CreateXYScalarPlot() function. For example, one of the CreateXYScalarPlot() functions is

The second argument of this function is the mathematical expression of the remaining power loss once the input line, output load, gate drive, and MOSFET power losses have been removed:

This expression is a good example of scalar mathematics that DVM evaluates on a point-by-point basis and then plots the resulting values.

The testplan for this schematic is available from  SIMPLIS_dvm_tutorial_examples.zip at this path: testplans/8.1_efficiency_and_powerloss.testplan.

Although this testplan is similar to the built-in efficiency testplan in 5.1 Running the Built-In Efficiency Testplan, it differs in the following ways:

• With the addition of a second input source, you now have two source columns.
• Measurement columns have been added for the scalar aliases.
• On the last line of the testplan is a single FinalProcess entry for the post-process script. with a path relative to the schematic: ..\scripts\8.1_efficiency_and_powerloss_post_process.sxscr
• Additional tests have been added for the lower load currents in order to fill in the efficiency curve points. This testplan uses 5% load steps from 5% to 40% of full load, and 10% load steps from 40% to 100% of full load.

After running 8.1_efficiency_and_powerloss.testplan on the  8.1_Sync Buck Efficiency.sxsch schematic, the overview test report shows five graphs:

• Efficiency
• Power losses in the high-side MOSFET
• Power losses in the low-side MOSFET
• High-side gate-drive power
• Remaining power

Applying this testplan to a new schematic:

• As mentioned previously, the source, load, and probe names on the schematic must match the names in the testplan Alias functions.
• To make these names match, you may change either the schematic or the testplan; the choice is up to you.
• This testplan expects the schematic to have two input sources. If you attempt to run this testplan on a schematic with one input source, DVM produces an error message and aborts the test run.

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