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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|10% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|10% Load |
| Date / Time | 2/7/2015 10:38:05 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\10% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.5424% |
| Frequency(CLK) | 100.25084kHertz |
| Power(LOAD) | 12.1099 |
| Power(SRC) | 12.6749 |
| eta_max | 95.5424% |
| gain_crossover_freq | 683.346 |
| gain_margin | 32.5624 |
| gmargin_max | 32.5624 |
| gxover_max | 683.346 |
| iload_max | 502.545m |
| min_phase | 109.748 |
| phase_crossover_freq | 46.8562k |
| min_phase_freq | 135.936 |
| phase_margin | 118.002 |
| pmargin_max | 118.002 |
| sw_freq_max | 100.25084kHertz |
| ICout | AVG 4.80608u MIN -502.445m MAX 510.833m RMS 375.437m |
| IDQ1 | AVG 31.6993m MIN -466.45m MAX 513.604m RMS 219.881m |
| IDQ2 | AVG 31.6593m MIN -470.67m MAX 512.685m RMS 219.884m |
| ILOAD | AVG 502.545m MIN 502.437m MAX 502.656m RMS 502.545m |
| ISRC | AVG 31.6993m MIN -466.45m MAX 513.604m RMS 219.881m |
| Im | AVG 8.78217u MIN -461.589m MAX 461.585m RMS 267.974m |
| Ip | AVG 31.2173u MIN -135.05m MAX 135.133m RMS 83.648m |
| Ir | AVG 39.9994u MIN -475.322m MAX 475.179m RMS 312.738m |
| Is1 | AVG 251.392m MIN -5.04714u MAX 1.01349 RMS 443.776m |
| Is2 | AVG 251.158m MIN -5.04714u MAX 1.01287 RMS 443.44m |
| VLOAD | AVG 24.0971 MIN 24.0921 MAX 24.1022 RMS 24.0971 |
| VSRC | AVG 399.997 MIN 399.949 MAX 400.047 RMS 399.997 |
| VSW | AVG 199.997 MIN -719.332m MAX 400.764 RMS 282.312 |
| Vs | AVG -10.1655m MIN -24.8401 MAX 24.7996 RMS 24.6446 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1022) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0921) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (32.5624) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (118.002) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac16_1029.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop16_995.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop16_985.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop16_976.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop16_990.sxgph |
| Other SXGPH Files | |
| default#1018#pop | simplis_pop16_1018.sxgph |
| Modulator#pop | simplis_pop16_1023.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac16_1036.sxgph |
