back to overview ▲
» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|15% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|15% Load |
| Date / Time | 2/7/2015 10:38:18 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\15% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.8367% |
| Frequency(CLK) | 98.95083kHertz |
| Power(LOAD) | 18.1584 |
| Power(SRC) | 18.9472 |
| eta_max | 95.8367% |
| gain_crossover_freq | 1.4611k |
| gain_margin | 31.578 |
| gmargin_max | 31.578 |
| gxover_max | 1.4611k |
| iload_max | 753.551m |
| min_phase | 113.289 |
| phase_crossover_freq | 44.4389k |
| min_phase_freq | 1.4611k |
| phase_margin | 113.23 |
| pmargin_max | 113.23 |
| sw_freq_max | 98.95083kHertz |
| ICout | AVG 4.79849u MIN -753.32m MAX 656.677m RMS 507.389m |
| IDQ1 | AVG 47.3823m MIN -475.406m MAX 548.077m RMS 239.089m |
| IDQ2 | AVG 47.3423m MIN -479.646m MAX 547.255m RMS 239.083m |
| ILOAD | AVG 753.551m MIN 753.312m MAX 753.762m RMS 753.551m |
| ISRC | AVG 47.3823m MIN -475.406m MAX 548.077m RMS 239.089m |
| Im | AVG -16.9992u MIN -469.98m MAX 469.937m RMS 271.882m |
| Ip | AVG 56.9983u MIN -187.919m MAX 188.06m RMS 121.14m |
| Ir | AVG 39.9991u MIN -512.232m MAX 512.079m RMS 339.84m |
| Is1 | AVG 376.992m MIN -5.05023u MAX 1.41044 RMS 642.737m |
| Is2 | AVG 376.564m MIN -5.05024u MAX 1.40939 RMS 642.145m |
| VLOAD | AVG 24.0971 MIN 24.0896 MAX 24.1037 RMS 24.0971 |
| VSRC | AVG 399.995 MIN 399.945 MAX 400.048 RMS 399.995 |
| VSW | AVG 199.996 MIN -720.103m MAX 400.766 RMS 282.331 |
| Vs | AVG -14.9457m MIN -24.8686 MAX 24.8123 RMS 24.7527 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1037) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0896) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (31.578) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (113.23) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac17_1094.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop17_1071.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop17_1061.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop17_1041.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop17_1066.sxgph |
| Other SXGPH Files | |
| default#1049#pop | simplis_pop17_1049.sxgph |
| Modulator#pop | simplis_pop17_1054.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac17_1101.sxgph |
