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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|20% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|20% Load |
| Date / Time | 2/7/2015 10:38:32 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\20% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.9577% |
| Frequency(CLK) | 98.102575kHertz |
| Power(LOAD) | 24.2067 |
| Power(SRC) | 25.2265 |
| eta_max | 95.9577% |
| gain_crossover_freq | 2.48014k |
| gain_margin | 30.7982 |
| gmargin_max | 30.7982 |
| gxover_max | 2.48014k |
| iload_max | 1.00456 |
| min_phase | 101.21 |
| phase_crossover_freq | 42.6554k |
| min_phase_freq | 2.48014k |
| phase_margin | 101.168 |
| pmargin_max | 101.168 |
| sw_freq_max | 98.102575kHertz |
| ICout | AVG 4.79729u MIN -1.00414 MAX 780.063m RMS 622.231m |
| IDQ1 | AVG 63.0826m MIN -481.55m MAX 575.317m RMS 256.7m |
| IDQ2 | AVG 63.0426m MIN -485.698m MAX 576.728m RMS 256.689m |
| ILOAD | AVG 1.00456 MIN 1.00413 MAX 1.00489 RMS 1.00456 |
| ISRC | AVG 63.0826m MIN -481.55m MAX 575.317m RMS 256.7m |
| Im | AVG -44.3349u MIN -475.064m MAX 474.97m RMS 274.463m |
| Ip | AVG 84.3337u MIN -237.793m MAX 237.995m RMS 157.574m |
| Ir | AVG 39.9988u MIN -544.155m MAX 544.016m RMS 364.701m |
| Is1 | AVG 502.596m MIN -5.0531u MAX 1.78496 RMS 836.093m |
| Is2 | AVG 501.964m MIN -5.05311u MAX 1.78344 RMS 835.225m |
| VLOAD | AVG 24.097 MIN 24.087 MAX 24.1048 RMS 24.097 |
| VSRC | AVG 399.994 MIN 399.942 MAX 400.048 RMS 399.994 |
| VSW | AVG 199.994 MIN -720.648m MAX 400.767 RMS 282.34 |
| Vs | AVG -20.0237m MIN -24.8953 MAX 24.824 RMS 24.8037 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1048) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.087) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (30.7982) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (101.168) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac18_1159.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop18_1125.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop18_1115.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop18_1106.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop18_1120.sxgph |
| Other SXGPH Files | |
| default#1148#pop | simplis_pop18_1148.sxgph |
| Modulator#pop | simplis_pop18_1153.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac18_1166.sxgph |
