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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|25% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|25% Load |
| Date / Time | 2/7/2015 10:38:44 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\25% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 96.0112% |
| Frequency(CLK) | 97.520849kHertz |
| Power(LOAD) | 30.2549 |
| Power(SRC) | 31.5119 |
| eta_max | 96.0112% |
| gain_crossover_freq | 3.45047k |
| gain_margin | 30.1637 |
| gmargin_max | 30.1637 |
| gxover_max | 3.45047k |
| iload_max | 1.25556 |
| min_phase | 86.516 |
| phase_crossover_freq | 41.2356k |
| min_phase_freq | 3.45047k |
| phase_margin | 86.4619 |
| pmargin_max | 86.4619 |
| sw_freq_max | 97.520849kHertz |
| ICout | AVG 4.79687u MIN -1.25491 MAX 885.053m RMS 720.631m |
| IDQ1 | AVG 78.7984m MIN -501.521m MAX 604.249m RMS 273.117m |
| IDQ2 | AVG 78.7584m MIN -501.917m MAX 603.419m RMS 273.102m |
| ILOAD | AVG 1.25556 MIN 1.2549 MAX 1.25602 RMS 1.25556 |
| ISRC | AVG 78.7984m MIN -501.521m MAX 604.249m RMS 273.117m |
| Im | AVG -70.7893u MIN -478.352m MAX 478.21m RMS 276.269m |
| Ip | AVG 110.788u MIN -285.218m MAX 285.478m RMS 193.049m |
| Ir | AVG 39.9985u MIN -573.328m MAX 573.203m RMS 387.874m |
| Is1 | AVG 628.196m MIN -5.05579u MAX 2.14108 RMS 1.02436 |
| Is2 | AVG 627.365m MIN -5.05581u MAX 2.13913 RMS 1.02322 |
| VLOAD | AVG 24.0968 MIN 24.0845 MAX 24.1057 RMS 24.0968 |
| VSRC | AVG 399.992 MIN 399.94 MAX 400.05 RMS 399.992 |
| VSW | AVG 199.992 MIN -721.014m MAX 400.768 RMS 282.34 |
| Vs | AVG -25.111m MIN -24.9205 MAX 24.835 RMS 24.8262 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1057) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0845) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (30.1637) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (86.4619) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac19_1224.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop19_1190.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop19_1180.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop19_1171.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop19_1185.sxgph |
| Other SXGPH Files | |
| default#1213#pop | simplis_pop19_1213.sxgph |
| Modulator#pop | simplis_pop19_1218.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac19_1231.sxgph |
