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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|30% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|30% Load |
| Date / Time | 2/7/2015 10:38:57 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\30% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 96.0248% |
| Frequency(CLK) | 97.041809kHertz |
| Power(LOAD) | 36.3029 |
| Power(SRC) | 37.8058 |
| eta_max | 96.0248% |
| gain_crossover_freq | 3.67299k |
| gain_margin | 29.3715 |
| gmargin_max | 29.3715 |
| gxover_max | 3.67299k |
| iload_max | 1.50655 |
| min_phase | 83.5981 |
| phase_crossover_freq | 38.9898k |
| min_phase_freq | 3.67299k |
| phase_margin | 83.3771 |
| pmargin_max | 83.3771 |
| sw_freq_max | 97.041809kHertz |
| ICout | AVG 4.79607u MIN -1.50562 MAX 984.943m RMS 813.787m |
| IDQ1 | AVG 94.5354m MIN -524.378m MAX 619.419m RMS 289.79m |
| IDQ2 | AVG 94.4954m MIN -521.767m MAX 620.906m RMS 289.77m |
| ILOAD | AVG 1.50655 MIN 1.50561 MAX 1.50718 RMS 1.50655 |
| ISRC | AVG 94.5354m MIN -524.378m MAX 619.419m RMS 289.79m |
| Im | AVG -72.9562u MIN -480.947m MAX 480.8m RMS 277.795m |
| Ip | AVG 112.954u MIN -332.013m MAX 332.284m RMS 228.34m |
| Ir | AVG 39.9982u MIN -602.841m MAX 602.731m RMS 411.404m |
| Is1 | AVG 753.702m MIN -5.05844u MAX 2.49212 RMS 1.21154 |
| Is2 | AVG 752.855m MIN -5.05846u MAX 2.4901 RMS 1.21036 |
| VLOAD | AVG 24.0967 MIN 24.0818 MAX 24.1065 RMS 24.0967 |
| VSRC | AVG 399.991 MIN 399.938 MAX 400.052 RMS 399.991 |
| VSW | AVG 199.991 MIN -721.289m MAX 400.77 RMS 282.337 |
| Vs | AVG -30.1311m MIN -24.9453 MAX 24.8458 RMS 24.8382 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1065) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0818) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (29.3715) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (83.3771) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac20_1289.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop20_1266.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop20_1256.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop20_1236.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop20_1261.sxgph |
| Other SXGPH Files | |
| default#1244#pop | simplis_pop20_1244.sxgph |
| Modulator#pop | simplis_pop20_1249.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac20_1296.sxgph |
