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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|35% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|35% Load |
| Date / Time | 2/7/2015 10:39:11 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\35% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 96.0083% |
| Frequency(CLK) | 96.594642kHertz |
| Power(LOAD) | 42.3505 |
| Power(SRC) | 44.1113 |
| eta_max | 96.0083% |
| gain_crossover_freq | 3.88338k |
| gain_margin | 28.5551 |
| gmargin_max | 28.5551 |
| gxover_max | 3.88338k |
| iload_max | 1.75754 |
| min_phase | 80.7505 |
| phase_crossover_freq | 36.8828k |
| min_phase_freq | 3.88338k |
| phase_margin | 80.6261 |
| pmargin_max | 80.6261 |
| sw_freq_max | 96.594642kHertz |
| ICout | AVG 4.79542u MIN -1.75627 MAX 1.08776 RMS 908.951m |
| IDQ1 | AVG 110.302m MIN -544.574m MAX 638.403m RMS 307.513m |
| IDQ2 | AVG 110.262m MIN -544.354m MAX 639.882m RMS 307.489m |
| ILOAD | AVG 1.75754 MIN 1.75626 MAX 1.75834 RMS 1.75754 |
| ISRC | AVG 110.302m MIN -544.574m MAX 638.403m RMS 307.513m |
| Im | AVG -74.9591u MIN -483.406m MAX 483.256m RMS 279.243m |
| Ip | AVG 114.957u MIN -379.202m MAX 379.481m RMS 263.866m |
| Ir | AVG 39.9978u MIN -634.407m MAX 634.311m RMS 436.418m |
| Is1 | AVG 879.203m MIN -5.0611u MAX 2.84611 RMS 1.39996 |
| Is2 | AVG 878.341m MIN -5.06112u MAX 2.84401 RMS 1.39875 |
| VLOAD | AVG 24.0965 MIN 24.0791 MAX 24.1074 RMS 24.0965 |
| VSRC | AVG 399.989 MIN 399.936 MAX 400.054 RMS 399.989 |
| VSW | AVG 199.989 MIN -721.58m MAX 400.773 RMS 282.332 |
| Vs | AVG -35.1509m MIN -24.9703 MAX 24.8567 RMS 24.8501 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1074) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0791) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (28.5551) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (80.6261) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac21_1354.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop21_1320.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop21_1310.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop21_1301.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop21_1315.sxgph |
| Other SXGPH Files | |
| default#1343#pop | simplis_pop21_1343.sxgph |
| Modulator#pop | simplis_pop21_1348.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac21_1361.sxgph |
