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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|60% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|60% Load |
| Date / Time | 2/7/2015 10:39:50 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\60% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.7404% |
| Frequency(CLK) | 94.728226kHertz |
| Power(LOAD) | 72.5823 |
| Power(SRC) | 75.8116 |
| eta_max | 95.7404% |
| gain_crossover_freq | 4.83157k |
| gain_margin | 24.2796 |
| gmargin_max | 24.2796 |
| gxover_max | 4.83157k |
| iload_max | 3.01236 |
| min_phase | 67.0477 |
| phase_crossover_freq | 28.4384k |
| min_phase_freq | 4.83157k |
| phase_margin | 66.8014 |
| pmargin_max | 66.8014 |
| sw_freq_max | 94.728226kHertz |
| ICout | AVG 4.79162u MIN -3.00862 MAX 1.63587 RMS 1.40591 |
| IDQ1 | AVG 189.57m MIN -632.858m MAX 815.909m RMS 407.293m |
| IDQ2 | AVG 189.53m MIN -632.613m MAX 815.955m RMS 407.261m |
| ILOAD | AVG 3.01236 MIN 3.00861 MAX 3.01442 RMS 3.01236 |
| ISRC | AVG 189.57m MIN -632.858m MAX 815.909m RMS 407.293m |
| Im | AVG -83.4591u MIN -494.098m MAX 493.931m RMS 285.565m |
| Ip | AVG 123.455u MIN -619.726m MAX 620.04m RMS 443.34m |
| Ir | AVG 39.9962u MIN -815.951m MAX 815.905m RMS 577.294m |
| Is1 | AVG 1.50664 MIN -5.07417u MAX 4.65029 RMS 2.35183 |
| Is2 | AVG 1.50572 MIN -5.07419u MAX 4.64794 RMS 2.35049 |
| VLOAD | AVG 24.0948 MIN 24.065 MAX 24.1112 RMS 24.0949 |
| VSRC | AVG 399.981 MIN 399.918 MAX 400.063 RMS 399.981 |
| VSW | AVG 199.981 MIN -727.503m MAX 400.789 RMS 282.288 |
| Vs | AVG -60.2472m MIN -25.0932 MAX 24.9073 RMS 24.9087 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1112) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.065) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (24.2796) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (66.8014) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac24_1549.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop24_1515.sxgph |
 SRC
ISRC
VSRC
|
|
| SXGPH File | simplis_pop24_1505.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop24_1496.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop24_1510.sxgph |
| Other SXGPH Files | |
| default#1538#pop | simplis_pop24_1538.sxgph |
| Modulator#pop | simplis_pop24_1543.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac24_1556.sxgph |
