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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|70% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|70% Load |
| Date / Time | 2/7/2015 10:40:02 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\70% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.6187% |
| Frequency(CLK) | 94.142447kHertz |
| Power(LOAD) | 84.6714 |
| Power(SRC) | 88.5511 |
| eta_max | 95.6187% |
| gain_crossover_freq | 5.17064k |
| gain_margin | 22.6043 |
| gmargin_max | 22.6043 |
| gxover_max | 5.17064k |
| iload_max | 3.51421 |
| min_phase | 61.6285 |
| phase_crossover_freq | 25.8905k |
| min_phase_freq | 5.17064k |
| phase_margin | 61.3474 |
| pmargin_max | 61.3474 |
| sw_freq_max | 94.142447kHertz |
| ICout | AVG 4.79001u MIN -3.50912 MAX 1.86718 RMS 1.61195 |
| IDQ1 | AVG 221.428m MIN -665.82m MAX 896.958m RMS 450.765m |
| IDQ2 | AVG 221.389m MIN -665.575m MAX 896.99m RMS 450.73m |
| ILOAD | AVG 3.51421 MIN 3.50911 MAX 3.51695 RMS 3.51421 |
| ISRC | AVG 221.428m MIN -665.82m MAX 896.958m RMS 450.765m |
| Im | AVG -86.5306u MIN -497.553m MAX 497.379m RMS 287.603m |
| Ip | AVG 126.526u MIN -717.56m MAX 717.885m RMS 515.636m |
| Ir | AVG 39.9956u MIN -896.986m MAX 896.954m RMS 638.694m |
| Is1 | AVG 1.75758 MIN -5.0781u MAX 5.38413 RMS 2.73526 |
| Is2 | AVG 1.75663 MIN -5.07812u MAX 5.3817 RMS 2.73388 |
| VLOAD | AVG 24.094 MIN 24.0592 MAX 24.1127 RMS 24.094 |
| VSRC | AVG 399.978 MIN 399.91 MAX 400.067 RMS 399.978 |
| VSW | AVG 199.978 MIN -729.801m MAX 400.795 RMS 282.265 |
| Vs | AVG -70.2843m MIN -25.1299 MAX 24.9147 RMS 24.9277 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1127) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0592) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (22.6043) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (61.3474) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac25_1614.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop25_1580.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop25_1570.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop25_1561.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop25_1575.sxgph |
| Other SXGPH Files | |
| DVM Bode Plot Input#log#ac | simplis_ac25_1621.sxgph |
| default#1603#pop | simplis_pop25_1603.sxgph |
| Modulator#pop | simplis_pop25_1608.sxgph |
