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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|90% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Maximum|90% Load |
| Date / Time | 2/7/2015 10:40:29 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\90% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.3713% |
| Frequency(CLK) | 93.149455kHertz |
| Power(LOAD) | 108.842 |
| Power(SRC) | 114.124 |
| eta_max | 95.3713% |
| gain_crossover_freq | 5.68428k |
| gain_margin | 19.6796 |
| gmargin_max | 19.6796 |
| gxover_max | 5.68428k |
| iload_max | 4.51775 |
| min_phase | 53.6011 |
| phase_crossover_freq | 22.0815k |
| min_phase_freq | 5.68428k |
| phase_margin | 53.2556 |
| pmargin_max | 53.2556 |
| sw_freq_max | 93.149455kHertz |
| ICout | AVG 4.78671u MIN -4.50933 MAX 2.34465 RMS 2.03295 |
| IDQ1 | AVG 285.384m MIN -727.188m MAX 1.0681 RMS 541.41m |
| IDQ2 | AVG 285.344m MIN -726.925m MAX 1.06812 RMS 541.372m |
| ILOAD | AVG 4.51775 MIN 4.50933 MAX 4.52217 RMS 4.51775 |
| ISRC | AVG 285.384m MIN -727.188m MAX 1.0681 RMS 541.41m |
| Im | AVG -91.3656u MIN -503.522m MAX 503.339m RMS 291.127m |
| Ip | AVG 131.36u MIN -915.236m MAX 915.577m RMS 660.756m |
| Ir | AVG 39.9943u MIN -1.06811 MAX 1.0681 RMS 766.751m |
| Is1 | AVG 2.25937 MIN -5.08601u MAX 6.86682 RMS 3.5049 |
| Is2 | AVG 2.25838 MIN -5.08603u MAX 6.86426 RMS 3.50347 |
| VLOAD | AVG 24.092 MIN 24.0472 MAX 24.1155 RMS 24.092 |
| VSRC | AVG 399.971 MIN 399.893 MAX 400.073 RMS 399.971 |
| VSW | AVG 199.972 MIN -734.07m MAX 400.805 RMS 282.212 |
| Vs | AVG -90.3551m MIN -25.2038 MAX 24.9293 RMS 24.9607 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1155) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0472) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (19.6796) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (53.2556) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac27_1744.sxgph |
 LOAD
ILOAD
VLOAD
|
|
| SXGPH File | simplis_pop27_1710.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop27_1700.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop27_1691.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop27_1705.sxgph |
| Other SXGPH Files | |
| default#1733#pop | simplis_pop27_1733.sxgph |
| Modulator#pop | simplis_pop27_1738.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac27_1751.sxgph |
