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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|10% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|10% Load |
| Date / Time | 2/7/2015 10:41:09 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\10% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 94.9780% |
| Frequency(CLK) | 80.856269kHertz |
| Power(LOAD) | 12.1079 |
| Power(SRC) | 12.7481 |
| eta_min | 94.9780% |
| gain_crossover_freq | 2.9502k |
| gain_margin | 27.3278 |
| gmargin_min | 27.3278 |
| gxover_min | 2.9502k |
| iload_min | 502.466m |
| min_phase | 92.821 |
| phase_crossover_freq | 34.3931k |
| min_phase_freq | 2.9502k |
| phase_margin | 92.7916 |
| pmargin_min | 92.7916 |
| sw_freq_min | 80.856269kHertz |
| ICout | AVG 4.81639u MIN -502.366m MAX 692.701m RMS 458.919m |
| IDQ1 | AVG 35.43m MIN -557.595m MAX 589.674m RMS 259.911m |
| IDQ2 | AVG 35.394m MIN -562.346m MAX 588.5m RMS 259.915m |
| ILOAD | AVG 502.466m MIN 502.357m MAX 502.616m RMS 502.466m |
| ISRC | AVG 35.43m MIN -557.595m MAX 589.674m RMS 259.911m |
| Im | AVG 1.79068u MIN -556.823m MAX 556.781m RMS 330.158m |
| Ip | AVG 34.2086u MIN -159.263m MAX 159.377m RMS 90.7435m |
| Ir | AVG 35.9993u MIN -556.823m MAX 556.781m RMS 368.904m |
| Is1 | AVG 251.364m MIN -5.04874u MAX 1.19532 RMS 481.447m |
| Is2 | AVG 251.107m MIN -5.04875u MAX 1.19447 RMS 481.028m |
| VLOAD | AVG 24.0969 MIN 24.0918 MAX 24.1038 RMS 24.0969 |
| VSRC | AVG 359.996 MIN 359.941 MAX 360.056 RMS 359.996 |
| VSW | AVG 179.996 MIN -726.519m MAX 360.781 RMS 254.234 |
| Vs | AVG -10.0552m MIN -24.8541 MAX 24.8063 RMS 24.0526 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1038) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0918) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (27.3278) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (92.7916) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac30_1939.sxgph |
 LOAD
ILOAD
VLOAD
|
|
| SXGPH File | simplis_pop30_1905.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop30_1895.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop30_1886.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop30_1900.sxgph |
| Other SXGPH Files | |
| default#1928#pop | simplis_pop30_1928.sxgph |
| Modulator#pop | simplis_pop30_1933.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac30_1946.sxgph |
