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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|100% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|100% Load |
| Date / Time | 2/7/2015 10:43:44 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\100% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.0497% |
| Frequency(CLK) | 78.332454kHertz |
| Power(LOAD) | 120.322 |
| Power(SRC) | 126.588 |
| eta_min | 95.0497% |
| gain_crossover_freq | 4.35094k |
| gain_margin | 16.1516 |
| gmargin_min | 16.1516 |
| gxover_min | 4.35094k |
| iload_min | 5.00691 |
| min_phase | 53.4346 |
| phase_crossover_freq | 13.4603k |
| min_phase_freq | 4.35094k |
| phase_margin | 52.9692 |
| pmargin_min | 52.9692 |
| sw_freq_min | 78.332454kHertz |
| ICout | AVG 4.79463u MIN -4.99658 MAX 3.63484 RMS 2.96253 |
| IDQ1 | AVG 351.737m MIN -545.621m MAX 1.25078 RMS 611.041m |
| IDQ2 | AVG 351.701m MIN -545.835m MAX 1.25072 RMS 611.005m |
| ILOAD | AVG 5.00691 MIN 4.99645 MAX 5.01452 RMS 5.00691 |
| ISRC | AVG 351.737m MIN -545.621m MAX 1.25078 RMS 611.041m |
| Im | AVG -104.937u MIN -559.72m MAX 559.506m RMS 343.121m |
| Ip | AVG 140.93u MIN -1.15281 MAX 1.15325 RMS 776.117m |
| Ir | AVG 35.993u MIN -1.25072 MAX 1.25077 RMS 864.666m |
| Is1 | AVG 2.50399 MIN -5.08492u MAX 8.64936 RMS 4.11682 |
| Is2 | AVG 2.50293 MIN -5.08495u MAX 8.64605 RMS 4.11513 |
| VLOAD | AVG 24.0311 MIN 23.981 MAX 24.0675 RMS 24.0311 |
| VSRC | AVG 359.965 MIN 359.875 MAX 360.055 RMS 359.965 |
| VSW | AVG 179.965 MIN -724.314m MAX 360.777 RMS 253.85 |
| Vs | AVG -100.141m MIN -25.2413 MAX 24.8955 RMS 23.9787 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.0675) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (23.981) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (16.1516) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (52.9692) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac42_2719.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop42_2685.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop42_2675.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop42_2666.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop42_2680.sxgph |
| Other SXGPH Files | |
| default#2708#pop | simplis_pop42_2708.sxgph |
| Modulator#pop | simplis_pop42_2713.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac42_2726.sxgph |
