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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|15% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|15% Load |
| Date / Time | 2/7/2015 10:41:22 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\15% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.4326% |
| Frequency(CLK) | 80.420422kHertz |
| Power(LOAD) | 18.1563 |
| Power(SRC) | 19.0253 |
| eta_min | 95.4326% |
| gain_crossover_freq | 4.33243k |
| gain_margin | 26.59 |
| gmargin_min | 26.59 |
| gxover_min | 4.33243k |
| iload_min | 753.473m |
| min_phase | 63.9979 |
| phase_crossover_freq | 32.444k |
| min_phase_freq | 4.33243k |
| phase_margin | 63.6871 |
| pmargin_min | 63.6871 |
| sw_freq_min | 80.420422kHertz |
| ICout | AVG 4.81578u MIN -753.243m MAX 892.831m RMS 623.34m |
| IDQ1 | AVG 52.8694m MIN -563.894m MAX 593.896m RMS 277.055m |
| IDQ2 | AVG 52.8334m MIN -568.087m MAX 592.963m RMS 277.053m |
| ILOAD | AVG 753.473m MIN 753.232m MAX 753.76m RMS 753.473m |
| ISRC | AVG 52.8694m MIN -563.894m MAX 593.896m RMS 277.055m |
| Im | AVG -25.1911u MIN -564.357m MAX 564.266m RMS 333.273m |
| Ip | AVG 61.19u MIN -219.357m MAX 219.547m RMS 130.404m |
| Ir | AVG 35.9989u MIN -564.357m MAX 564.266m RMS 393.073m |
| Is1 | AVG 376.968m MIN -5.05233u MAX 1.6466 RMS 691.931m |
| Is2 | AVG 376.509m MIN -5.05235u MAX 1.64517 RMS 691.208m |
| VLOAD | AVG 24.0968 MIN 24.0893 MAX 24.1058 RMS 24.0969 |
| VSRC | AVG 359.995 MIN 359.941 MAX 360.056 RMS 359.995 |
| VSW | AVG 179.995 MIN -727.037m MAX 360.782 RMS 254.217 |
| Vs | AVG -15.0425m MIN -24.8869 MAX 24.8211 RMS 24.2426 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1058) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0893) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (26.59) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (63.6871) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac31_2004.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop31_1970.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop31_1960.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop31_1951.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop31_1965.sxgph |
| Other SXGPH Files | |
| default#1993#pop | simplis_pop31_1993.sxgph |
| Modulator#pop | simplis_pop31_1998.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac31_2011.sxgph |
