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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|20% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|20% Load |
| Date / Time | 2/7/2015 10:41:35 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\20% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.6362% |
| Frequency(CLK) | 80.173989kHertz |
| Power(LOAD) | 24.2048 |
| Power(SRC) | 25.3093 |
| eta_min | 95.6362% |
| gain_crossover_freq | 4.73763k |
| gain_margin | 26.2307 |
| gmargin_min | 26.2307 |
| gxover_min | 4.73763k |
| iload_min | 1.00448 |
| min_phase | 49.896 |
| phase_crossover_freq | 31.6165k |
| min_phase_freq | 4.73763k |
| phase_margin | 49.7419 |
| pmargin_min | 49.7419 |
| sw_freq_min | 80.173989kHertz |
| ICout | AVG 4.81508u MIN -1.00407 MAX 1.06407 RMS 769.705m |
| IDQ1 | AVG 70.3273m MIN -567.354m MAX 596.68m RMS 292.909m |
| IDQ2 | AVG 70.2913m MIN -570.907m MAX 595.94m RMS 292.903m |
| ILOAD | AVG 1.00448 MIN 1.00406 MAX 1.00493 RMS 1.00448 |
| ISRC | AVG 70.3273m MIN -567.354m MAX 596.68m RMS 292.909m |
| Im | AVG -55.2086u MIN -568.904m MAX 568.761m RMS 335.056m |
| Ip | AVG 91.2072u MIN -275.598m MAX 275.868m RMS 168.758m |
| Ir | AVG 35.9986u MIN -568.904m MAX 568.761m RMS 415.428m |
| Is1 | AVG 502.585m MIN -5.05566u MAX 2.06901 RMS 895.497m |
| Is2 | AVG 501.901m MIN -5.05568u MAX 2.06698 RMS 894.446m |
| VLOAD | AVG 24.0968 MIN 24.0868 MAX 24.1075 RMS 24.0968 |
| VSRC | AVG 359.993 MIN 359.94 MAX 360.057 RMS 359.993 |
| VSW | AVG 179.993 MIN -727.333m MAX 360.783 RMS 254.199 |
| Vs | AVG -20.0861m MIN -24.9174 MAX 24.8348 RMS 24.3632 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1075) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0868) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (26.2307) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (49.7419) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac32_2069.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop32_2035.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop32_2025.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop32_2016.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop32_2030.sxgph |
| Other SXGPH Files | |
| default#2058#pop | simplis_pop32_2058.sxgph |
| Modulator#pop | simplis_pop32_2063.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac32_2076.sxgph |
