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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|25% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|25% Load |
| Date / Time | 2/7/2015 10:41:48 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\25% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.7371% |
| Frequency(CLK) | 80.005212kHertz |
| Power(LOAD) | 30.2532 |
| Power(SRC) | 31.6003 |
| eta_min | 95.7371% |
| gain_crossover_freq | 4.84903k |
| gain_margin | 26.1537 |
| gmargin_min | 26.1537 |
| gxover_min | 4.84903k |
| iload_min | 1.25549 |
| min_phase | 44.7731 |
| phase_crossover_freq | 31.4433k |
| min_phase_freq | 4.84903k |
| phase_margin | 44.5241 |
| pmargin_min | 44.5241 |
| sw_freq_min | 80.005212kHertz |
| ICout | AVG 4.81467u MIN -1.25484 MAX 1.21601 RMS 902.621m |
| IDQ1 | AVG 87.8049m MIN -568.933m MAX 602.49m RMS 307.796m |
| IDQ2 | AVG 87.7689m MIN -571.754m MAX 601.827m RMS 307.786m |
| ILOAD | AVG 1.25549 MIN 1.25483 MAX 1.25613 RMS 1.25549 |
| ISRC | AVG 87.8049m MIN -568.933m MAX 602.49m RMS 307.796m |
| Im | AVG -86.8831u MIN -571.474m MAX 571.277m RMS 336.189m |
| Ip | AVG 122.881u MIN -329.27m MAX 329.62m RMS 206.209m |
| Ir | AVG 35.9983u MIN -599.814m MAX 599.712m RMS 436.424m |
| Is1 | AVG 628.206m MIN -5.0588u MAX 2.47214 RMS 1.09428 |
| Is2 | AVG 627.285m MIN -5.05882u MAX 2.46952 RMS 1.09289 |
| VLOAD | AVG 24.0968 MIN 24.0843 MAX 24.109 RMS 24.0968 |
| VSRC | AVG 359.991 MIN 359.94 MAX 360.057 RMS 359.991 |
| VSW | AVG 179.991 MIN -727.481m MAX 360.783 RMS 254.179 |
| Vs | AVG -25.0886m MIN -24.9464 MAX 24.8477 RMS 24.4274 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.109) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0843) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (26.1537) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (44.5241) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac33_2134.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop33_2100.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop33_2090.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop33_2081.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop33_2095.sxgph |
| Other SXGPH Files | |
| default#2123#pop | simplis_pop33_2123.sxgph |
| Modulator#pop | simplis_pop33_2128.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac33_2141.sxgph |
