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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|40% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|40% Load |
| Date / Time | 2/7/2015 10:42:27 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\40% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.7958% |
| Frequency(CLK) | 79.572379kHertz |
| Power(LOAD) | 48.3912 |
| Power(SRC) | 50.5149 |
| eta_min | 95.7958% |
| gain_crossover_freq | 4.8037k |
| gain_margin | 25.1213 |
| gmargin_min | 25.1213 |
| gxover_min | 4.8037k |
| iload_min | 2.00835 |
| min_phase | 46.3592 |
| phase_crossover_freq | 27.9407k |
| min_phase_freq | 4.8037k |
| phase_margin | 46.1121 |
| pmargin_min | 46.1121 |
| sw_freq_min | 79.572379kHertz |
| ICout | AVG 4.81295u MIN -2.0067 MAX 1.62405 RMS 1.26363 |
| IDQ1 | AVG 140.353m MIN -569.904m MAX 692.871m RMS 350.926m |
| IDQ2 | AVG 140.317m MIN -567.133m MAX 692.911m RMS 350.908m |
| ILOAD | AVG 2.00835 MIN 2.00668 MAX 2.00972 RMS 2.00835 |
| ISRC | AVG 140.353m MIN -569.904m MAX 692.871m RMS 350.926m |
| Im | AVG -131.379u MIN -572.305m MAX 572.035m RMS 338.403m |
| Ip | AVG 167.377u MIN -484.034m MAX 484.504m RMS 316.453m |
| Ir | AVG 35.9972u MIN -692.908m MAX 692.868m RMS 497.269m |
| Is1 | AVG 1.00481 MIN -5.06743u MAX 3.63378 RMS 1.67919 |
| Is2 | AVG 1.00355 MIN -5.06747u MAX 3.63025 RMS 1.6773 |
| VLOAD | AVG 24.0949 MIN 24.075 MAX 24.1112 RMS 24.0949 |
| VSRC | AVG 359.986 MIN 359.931 MAX 360.057 RMS 359.986 |
| VSW | AVG 179.986 MIN -727.22m MAX 360.783 RMS 254.115 |
| Vs | AVG -40.1417m MIN -25.0279 MAX 24.8828 RMS 24.383 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1112) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.075) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (25.1213) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (46.1121) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac36_2329.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop36_2295.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop36_2285.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop36_2276.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop36_2290.sxgph |
| Other SXGPH Files | |
| Modulator#pop | simplis_pop36_2323.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac36_2336.sxgph |
| default#2318#pop | simplis_pop36_2318.sxgph |
