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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|5% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|5% Load |
| Date / Time | 2/7/2015 10:40:56 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\5% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 93.5499% |
| Frequency(CLK) | 81.797455kHertz |
| Power(LOAD) | 6.05942 |
| Power(SRC) | 6.47721 |
| eta_min | 93.5499% |
| gain_crossover_freq | 838.986 |
| gain_margin | 28.712 |
| gmargin_min | 28.712 |
| gxover_min | 838.986 |
| iload_min | 251.461m |
| min_phase | 97.9727 |
| phase_crossover_freq | 38.3577k |
| min_phase_freq | 92.3644 |
| phase_margin | 116.172 |
| pmargin_min | 116.172 |
| sw_freq_min | 81.797455kHertz |
| ICout | AVG 4.81732u MIN -251.439m MAX 442.326m RMS 267.086m |
| IDQ1 | AVG 18.0083m MIN -545.855m MAX 570.314m RMS 240.624m |
| IDQ2 | AVG 17.9723m MIN -551.103m MAX 574.496m RMS 240.63m |
| ILOAD | AVG 251.461m MIN 251.432m MAX 251.51m RMS 251.461m |
| ISRC | AVG 18.0083m MIN -545.855m MAX 570.314m RMS 240.624m |
| Im | AVG 23.4432u MIN -543.557m MAX 543.557m RMS 323.898m |
| Ip | AVG 12.5564u MIN -92.4654m MAX 92.5129m RMS 48.9155m |
| Ir | AVG 35.9996u MIN -543.557m MAX 543.557m RMS 341.718m |
| Is1 | AVG 125.78m MIN -5.0447u MAX 693.841m RMS 259.494m |
| Is2 | AVG 125.686m MIN -5.0447u MAX 693.485m RMS 259.329m |
| VLOAD | AVG 24.0969 MIN 24.0943 MAX 24.1013 RMS 24.0969 |
| VSRC | AVG 359.998 MIN 359.943 MAX 360.055 RMS 359.998 |
| VSW | AVG 179.998 MIN -725.573m MAX 360.779 RMS 254.245 |
| Vs | AVG -5.02997m MIN -24.8174 MAX 24.7896 RMS 23.7589 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1013) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0943) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (28.712) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (116.172) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac29_1874.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop29_1840.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop29_1830.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop29_1821.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop29_1835.sxgph |
| Other SXGPH Files | |
| default#1863#pop | simplis_pop29_1863.sxgph |
| Modulator#pop | simplis_pop29_1868.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac29_1881.sxgph |
