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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|50% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|50% Load |
| Date / Time | 2/7/2015 10:42:39 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\50% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.7118% |
| Frequency(CLK) | 79.293467kHertz |
| Power(LOAD) | 60.4653 |
| Power(SRC) | 63.1743 |
| eta_min | 95.7118% |
| gain_crossover_freq | 4.73587k |
| gain_margin | 23.3309 |
| gmargin_min | 23.3309 |
| gxover_min | 4.73587k |
| iload_min | 2.5099 |
| min_phase | 48.4238 |
| phase_crossover_freq | 23.6863k |
| min_phase_freq | 4.73587k |
| phase_margin | 48.2373 |
| pmargin_min | 48.2373 |
| sw_freq_min | 79.293467kHertz |
| ICout | AVG 4.81122u MIN -2.50731 MAX 1.92275 RMS 1.52329 |
| IDQ1 | AVG 175.526m MIN -567.321m MAX 767.712m RMS 385.655m |
| IDQ2 | AVG 175.49m MIN -564.831m MAX 767.721m RMS 385.632m |
| ILOAD | AVG 2.5099 MIN 2.50727 MAX 2.51192 RMS 2.5099 |
| ISRC | AVG 175.526m MIN -567.321m MAX 767.712m RMS 385.655m |
| Im | AVG -128.428u MIN -571.447m MAX 571.184m RMS 339.682m |
| Ip | AVG 164.425u MIN -590.815m MAX 591.29m RMS 391.576m |
| Ir | AVG 35.9965u MIN -767.718m MAX 767.708m RMS 546.285m |
| Is1 | AVG 1.25557 MIN -5.07283u MAX 4.43467 RMS 2.07759 |
| Is2 | AVG 1.25433 MIN -5.07286u MAX 4.43111 RMS 2.0757 |
| VLOAD | AVG 24.0907 MIN 24.0657 MAX 24.11 RMS 24.0908 |
| VSRC | AVG 359.982 MIN 359.923 MAX 360.057 RMS 359.982 |
| VSW | AVG 179.983 MIN -726.833m MAX 360.782 RMS 254.072 |
| Vs | AVG -50.1662m MIN -25.0814 MAX 24.9043 RMS 24.3147 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.11) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0657) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (23.3309) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (48.2373) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac37_2394.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop37_2360.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop37_2350.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop37_2341.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop37_2355.sxgph |
| Other SXGPH Files | |
| default#2383#pop | simplis_pop37_2383.sxgph |
| Modulator#pop | simplis_pop37_2388.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac37_2401.sxgph |
