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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|60% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|60% Load |
| Date / Time | 2/7/2015 10:42:53 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\60% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.6023% |
| Frequency(CLK) | 79.055846kHertz |
| Power(LOAD) | 72.5135 |
| Power(SRC) | 75.8492 |
| eta_min | 95.6023% |
| gain_crossover_freq | 4.7144k |
| gain_margin | 21.3369 |
| gmargin_min | 21.3369 |
| gxover_min | 4.7144k |
| iload_min | 3.0109 |
| min_phase | 47.882 |
| phase_crossover_freq | 20.1384k |
| min_phase_freq | 4.7144k |
| phase_margin | 47.718 |
| pmargin_min | 47.718 |
| sw_freq_min | 79.055846kHertz |
| ICout | AVG 4.80893u MIN -3.00717 MAX 2.24238 RMS 1.79697 |
| IDQ1 | AVG 210.742m MIN -562.228m MAX 852.619m RMS 425.052m |
| IDQ2 | AVG 210.706m MIN -562.272m MAX 852.604m RMS 425.023m |
| ILOAD | AVG 3.0109 MIN 3.00713 MAX 3.01373 RMS 3.0109 |
| ISRC | AVG 210.742m MIN -562.228m MAX 852.619m RMS 425.052m |
| Im | AVG -125.437u MIN -569.95m MAX 569.694m RMS 340.674m |
| Ip | AVG 161.433u MIN -700.339m MAX 700.815m RMS 467.672m |
| Ir | AVG 35.9958u MIN -852.6m MAX 852.615m RMS 601.908m |
| Is1 | AVG 1.50606 MIN -5.07611u MAX 5.25611 RMS 2.48114 |
| Is2 | AVG 1.50485 MIN -5.07614u MAX 5.25254 RMS 2.47926 |
| VLOAD | AVG 24.0837 MIN 24.0536 MAX 24.1062 RMS 24.0837 |
| VSRC | AVG 359.979 MIN 359.915 MAX 360.056 RMS 359.979 |
| VSW | AVG 179.979 MIN -726.396m MAX 360.781 RMS 254.028 |
| Vs | AVG -60.1814m MIN -25.1171 MAX 24.9071 RMS 24.2435 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1062) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0536) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (21.3369) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (47.718) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac38_2459.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop38_2425.sxgph |
 SRC
ISRC
VSRC
|
|
| SXGPH File | simplis_pop38_2415.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop38_2406.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop38_2420.sxgph |
| Other SXGPH Files | |
| default#2448#pop | simplis_pop38_2448.sxgph |
| Modulator#pop | simplis_pop38_2453.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac38_2466.sxgph |
