back to overview ▲
» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|70% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|70% Load |
| Date / Time | 2/7/2015 10:43:05 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\70% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.4789% |
| Frequency(CLK) | 78.849949kHertz |
| Power(LOAD) | 84.5286 |
| Power(SRC) | 88.5312 |
| eta_min | 95.4789% |
| gain_crossover_freq | 4.63969k |
| gain_margin | 19.6913 |
| gmargin_min | 19.6913 |
| gxover_min | 4.63969k |
| iload_min | 3.51122 |
| min_phase | 49.0723 |
| phase_crossover_freq | 17.6783k |
| min_phase_freq | 4.63969k |
| phase_margin | 49.0675 |
| pmargin_min | 49.0675 |
| sw_freq_min | 78.849949kHertz |
| ICout | AVG 4.80609u MIN -3.50614 MAX 2.5766 RMS 2.07993 |
| IDQ1 | AVG 245.981m MIN -559.237m MAX 944.961m RMS 468.025m |
| IDQ2 | AVG 245.945m MIN -559.69m MAX 944.931m RMS 467.994m |
| ILOAD | AVG 3.51122 MIN 3.50608 MAX 3.515 RMS 3.51122 |
| ISRC | AVG 245.981m MIN -559.237m MAX 944.961m RMS 468.025m |
| Im | AVG -121.234u MIN -567.934m MAX 567.686m RMS 341.448m |
| Ip | AVG 157.229u MIN -811.743m MAX 812.214m RMS 544.345m |
| Ir | AVG 35.9951u MIN -944.927m MAX 944.957m RMS 662.6m |
| Is1 | AVG 1.7562 MIN -5.07891u MAX 6.0916 RMS 2.88774 |
| Is2 | AVG 1.75502 MIN -5.07894u MAX 6.08807 RMS 2.8859 |
| VLOAD | AVG 24.0739 MIN 24.0388 MAX 24.0997 RMS 24.0739 |
| VSRC | AVG 359.975 MIN 359.906 MAX 360.056 RMS 359.975 |
| VSW | AVG 179.976 MIN -725.92m MAX 360.78 RMS 253.984 |
| Vs | AVG -70.252m MIN -25.1508 MAX 24.9073 RMS 24.1723 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.0997) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0388) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (19.6913) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (49.0675) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac39_2524.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop39_2490.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop39_2480.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop39_2471.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop39_2485.sxgph |
| Other SXGPH Files | |
| DVM Bode Plot Input#log#ac | simplis_ac39_2531.sxgph |
| default#2513#pop | simplis_pop39_2513.sxgph |
| Modulator#pop | simplis_pop39_2518.sxgph |
