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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|80% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|80% Load |
| Date / Time | 2/7/2015 10:43:17 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\80% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.3440% |
| Frequency(CLK) | 78.663833kHertz |
| Power(LOAD) | 96.5045 |
| Power(SRC) | 101.217 |
| eta_min | 95.3440% |
| gain_crossover_freq | 4.54921k |
| gain_margin | 18.2986 |
| gmargin_min | 18.2986 |
| gxover_min | 4.54921k |
| iload_min | 4.01071 |
| min_phase | 50.5666 |
| phase_crossover_freq | 15.9072k |
| min_phase_freq | 4.54921k |
| phase_margin | 50.3544 |
| pmargin_min | 50.3544 |
| sw_freq_min | 78.663833kHertz |
| ICout | AVG 4.80259u MIN -4.00409 MAX 2.92163 RMS 2.36954 |
| IDQ1 | AVG 281.232m MIN -557.633m MAX 1.04289 RMS 513.738m |
| IDQ2 | AVG 281.196m MIN -556.978m MAX 1.04285 RMS 513.705m |
| ILOAD | AVG 4.01071 MIN 4.00401 MAX 4.01561 RMS 4.01072 |
| ISRC | AVG 281.232m MIN -557.633m MAX 1.04289 RMS 513.738m |
| Im | AVG -116.324u MIN -565.516m MAX 565.279m RMS 342.089m |
| Ip | AVG 152.318u MIN -924.504m MAX 924.967m RMS 621.389m |
| Ir | AVG 35.9944u MIN -1.04285 MAX 1.04289 RMS 727.176m |
| Is1 | AVG 2.00593 MIN -5.08129u MAX 6.93725 RMS 3.29631 |
| Is2 | AVG 2.00479 MIN -5.08131u MAX 6.93377 RMS 3.29451 |
| VLOAD | AVG 24.0617 MIN 24.0216 MAX 24.0909 RMS 24.0617 |
| VSRC | AVG 359.972 MIN 359.896 MAX 360.056 RMS 359.972 |
| VSW | AVG 179.972 MIN -725.412m MAX 360.779 RMS 253.94 |
| Vs | AVG -80.2357m MIN -25.1826 MAX 24.9053 RMS 24.1032 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.0909) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0216) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (18.2986) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (50.3544) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac40_2589.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop40_2555.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop40_2545.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop40_2536.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop40_2550.sxgph |
| Other SXGPH Files | |
| default#2578#pop | simplis_pop40_2578.sxgph |
| Modulator#pop | simplis_pop40_2583.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac40_2596.sxgph |
