back to overview ▲
» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|90% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Minimum|90% Load |
| Date / Time | 2/7/2015 10:43:31 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\90% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.1999% |
| Frequency(CLK) | 78.492365kHertz |
| Power(LOAD) | 108.437 |
| Power(SRC) | 113.904 |
| eta_min | 95.1999% |
| gain_crossover_freq | 4.45169k |
| gain_margin | 17.151 |
| gmargin_min | 17.151 |
| gxover_min | 4.45169k |
| iload_min | 4.50931 |
| min_phase | 52.0485 |
| phase_crossover_freq | 14.5165k |
| min_phase_freq | 4.45169k |
| phase_margin | 51.673 |
| pmargin_min | 51.673 |
| sw_freq_min | 78.492365kHertz |
| ICout | AVG 4.79882u MIN -4.50094 MAX 3.27496 RMS 2.66413 |
| IDQ1 | AVG 316.489m MIN -551.006m MAX 1.14515 RMS 561.566m |
| IDQ2 | AVG 316.453m MIN -551.597m MAX 1.1451 RMS 561.532m |
| ILOAD | AVG 4.50931 MIN 4.50083 MAX 4.51548 RMS 4.50931 |
| ISRC | AVG 316.489m MIN -551.006m MAX 1.14515 RMS 561.566m |
| Im | AVG -110.868u MIN -562.763m MAX 562.537m RMS 342.638m |
| Ip | AVG 146.862u MIN -1.03827 MAX 1.03873 RMS 698.675m |
| Ir | AVG 35.9937u MIN -1.1451 MAX 1.14514 RMS 794.752m |
| Is1 | AVG 2.25521 MIN -5.08328u MAX 7.79045 RMS 3.70616 |
| Is2 | AVG 2.25411 MIN -5.0833u MAX 7.78705 RMS 3.70441 |
| VLOAD | AVG 24.0473 MIN 24.0022 MAX 24.0801 RMS 24.0473 |
| VSRC | AVG 359.968 MIN 359.885 MAX 360.055 RMS 359.968 |
| VSW | AVG 179.968 MIN -724.876m MAX 360.778 RMS 253.895 |
| Vs | AVG -90.1992m MIN -25.2127 MAX 24.9013 RMS 24.0381 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.0801) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0022) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (17.151) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (51.673) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac41_2654.sxgph |
 LOAD
ILOAD
VLOAD
|
|
| SXGPH File | simplis_pop41_2620.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop41_2610.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop41_2601.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop41_2615.sxgph |
| Other SXGPH Files | |
| default#2643#pop | simplis_pop41_2643.sxgph |
| Modulator#pop | simplis_pop41_2648.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac41_2661.sxgph |
