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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|10% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|10% Load |
| Date / Time | 2/7/2015 10:35:01 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\10% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.2584% |
| Frequency(CLK) | 89.052062kHertz |
| Power(LOAD) | 12.1087 |
| Power(SRC) | 12.7114 |
| eta_nom | 95.2584% |
| gain_crossover_freq | 1.71205k |
| gain_margin | 29.2597 |
| gmargin_nom | 29.2597 |
| gxover_nom | 1.71205k |
| iload_nom | 502.5m |
| min_phase | 109.687 |
| phase_crossover_freq | 38.4305k |
| min_phase_freq | 1.71205k |
| phase_margin | 109.61 |
| pmargin_nom | 109.61 |
| sw_freq_nom | 89.052062kHertz |
| ICout | AVG 4.81671u MIN -502.399m MAX 606.423m RMS 420.954m |
| IDQ1 | AVG 33.4664m MIN -515.434m MAX 542.427m RMS 241.077m |
| IDQ2 | AVG 33.4284m MIN -520.001m MAX 541.374m RMS 241.079m |
| ILOAD | AVG 502.5m MIN 502.391m MAX 502.631m RMS 502.5m |
| ISRC | AVG 33.4664m MIN -515.434m MAX 542.427m RMS 241.077m |
| Im | AVG 3.80088u MIN -512.877m MAX 512.849m RMS 301.072m |
| Ip | AVG 34.1984u MIN -147.769m MAX 147.875m RMS 87.4121m |
| Ir | AVG 37.9993u MIN -512.877m MAX 512.849m RMS 342.453m |
| Is1 | AVG 251.38m MIN -5.04798u MAX 1.10906 RMS 463.772m |
| Is2 | AVG 251.124m MIN -5.04799u MAX 1.10826 RMS 463.368m |
| VLOAD | AVG 24.097 MIN 24.0919 MAX 24.103 RMS 24.097 |
| VSRC | AVG 379.997 MIN 379.946 MAX 380.052 RMS 379.997 |
| VSW | AVG 189.997 MIN -723.2m MAX 380.773 RMS 268.293 |
| Vs | AVG -10.0448m MIN -24.8474 MAX 24.8031 RMS 24.3683 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.103) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0919) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (29.2597) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (109.61) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac2_119.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop2_85.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop2_75.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop2_66.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop2_80.sxgph |
| Other SXGPH Files | |
| default#108#pop | simplis_pop2_108.sxgph |
| Modulator#pop | simplis_pop2_113.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac2_126.sxgph |
