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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|100% Load

Test Details
Schematic 8.2_LLCClosed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|100% Load
Date / Time 2/7/2015 10:37:38 AM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\100% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.2077%
Frequency(CLK) 85.527204kHertz
Power(LOAD) 120.834
Power(SRC) 126.916
eta_nom 95.2077%
gain_crossover_freq 4.815k
gain_margin 16.4092
gmargin_nom 16.4092
gxover_nom 4.815k
iload_nom 5.01757
min_phase 42.6092
phase_crossover_freq 14.9472k
min_phase_freq 4.815k
phase_margin 42.2799
pmargin_nom 42.2799
sw_freq_nom 85.527204kHertz
ICout
AVG
4.79423u
MIN
-5.00716
MAX
2.96601
RMS
2.48077
IDQ1
AVG
334.081m
MIN
-537.357m
MAX
1.17798
RMS
590.815m
IDQ2
AVG
334.043m
MIN
-537.131m
MAX
1.17795
RMS
590.777m
ILOAD
AVG
5.01757
MIN
5.00715
MAX
5.02378
RMS
5.01757
ISRC
AVG
334.081m
MIN
-537.357m
MAX
1.17798
RMS
590.815m
Im
AVG
-118.505u
MIN
-548.416m
MAX
548.177m
RMS
317.269m
Ip
AVG
156.499u
MIN
-1.06487
MAX
1.06531
RMS
746.621m
Ir
AVG
37.9934u
MIN
-1.17795
MAX
1.17798
RMS
836.156m
Is1
AVG
2.50937
MIN
-5.0908u
MAX
7.9898
RMS
3.96044
Is2
AVG
2.5082
MIN
-5.09083u
MAX
7.98651
RMS
3.95866
VLOAD
AVG
24.0821
MIN
24.0322
MAX
24.1118
RMS
24.0821
VSRC
AVG
379.967
MIN
379.882
MAX
380.054
RMS
379.967
VSW
AVG
189.967
MIN
-723.75m
MAX
380.775
RMS
267.961
Vs
AVG
-100.331m
MIN
-25.254
MAX
24.9346
RMS
24.9611
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1118) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0322) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (16.4092) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (42.2799) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac14_899.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop14_865.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop14_855.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop14_846.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop14_860.sxgph
Other SXGPH Files
default#888#pop simplis_pop14_888.sxgph
Modulator#pop simplis_pop14_893.sxgph
DVM Bode Plot Input#log#ac simplis_ac14_906.sxgph