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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|20% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|20% Load |
| Date / Time | 2/7/2015 10:35:28 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\20% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.7967% |
| Frequency(CLK) | 87.967081kHertz |
| Power(LOAD) | 24.2057 |
| Power(SRC) | 25.2678 |
| eta_nom | 95.7967% |
| gain_crossover_freq | 4.28593k |
| gain_margin | 27.6259 |
| gmargin_nom | 27.6259 |
| gxover_nom | 4.28593k |
| iload_nom | 1.00451 |
| min_phase | 64.4503 |
| phase_crossover_freq | 34.1001k |
| min_phase_freq | 4.28593k |
| phase_margin | 64.1252 |
| pmargin_nom | 64.1252 |
| sw_freq_nom | 87.967081kHertz |
| ICout | AVG 4.81303u MIN -1.0041 MAX 918.349m RMS 692.71m |
| IDQ1 | AVG 66.5142m MIN -527.408m MAX 562.148m RMS 275.854m |
| IDQ2 | AVG 66.4762m MIN -531.272m MAX 571.287m RMS 275.849m |
| ILOAD | AVG 1.00451 MIN 1.00409 MAX 1.00491 RMS 1.00451 |
| ISRC | AVG 66.5142m MIN -527.408m MAX 562.148m RMS 275.854m |
| Im | AVG -46.8461u MIN -527.114m MAX 526.996m RMS 306.045m |
| Ip | AVG 84.8448u MIN -256.204m MAX 256.435m RMS 162.718m |
| Ir | AVG 37.9987u MIN -555.624m MAX 555.49m RMS 391.462m |
| Is1 | AVG 502.578m MIN -5.05435u MAX 1.92326 RMS 863.407m |
| Is2 | AVG 501.942m MIN -5.05437u MAX 1.92152 RMS 862.468m |
| VLOAD | AVG 24.0969 MIN 24.087 MAX 24.1062 RMS 24.0969 |
| VSRC | AVG 379.993 MIN 379.944 MAX 380.053 RMS 379.993 |
| VSW | AVG 189.994 MIN -724.185m MAX 380.776 RMS 268.267 |
| Vs | AVG -20.1193m MIN -24.9061 MAX 24.8293 RMS 24.7109 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1062) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.087) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (27.6259) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (64.1252) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac4_249.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop4_215.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop4_205.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop4_196.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop4_210.sxgph |
| Other SXGPH Files | |
| default#238#pop | simplis_pop4_238.sxgph |
| Modulator#pop | simplis_pop4_243.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac4_256.sxgph |
