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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|25% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|25% Load |
| Date / Time | 2/7/2015 10:35:40 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\25% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.8768% |
| Frequency(CLK) | 87.704081kHertz |
| Power(LOAD) | 30.2543 |
| Power(SRC) | 31.5554 |
| eta_nom | 95.8768% |
| gain_crossover_freq | 4.62713k |
| gain_margin | 27.3682 |
| gmargin_nom | 27.3682 |
| gxover_nom | 4.62713k |
| iload_nom | 1.25552 |
| min_phase | 53.838 |
| phase_crossover_freq | 33.6327k |
| min_phase_freq | 4.62713k |
| phase_margin | 53.811 |
| pmargin_nom | 53.811 |
| sw_freq_nom | 87.704081kHertz |
| ICout | AVG 4.80543u MIN -1.25488 MAX 1.0429 RMS 804.988m |
| IDQ1 | AVG 83.0628m MIN -530.087m MAX 585.954m RMS 291.508m |
| IDQ2 | AVG 83.0248m MIN -533.576m MAX 586.072m RMS 291.498m |
| ILOAD | AVG 1.25552 MIN 1.25487 MAX 1.25608 RMS 1.25552 |
| ISRC | AVG 83.0628m MIN -530.087m MAX 585.954m RMS 291.508m |
| Im | AVG -76.052u MIN -530.814m MAX 530.648m RMS 307.224m |
| Ip | AVG 114.05u MIN -306.232m MAX 306.531m RMS 198.889m |
| Ir | AVG 37.9984u MIN -586.068m MAX 585.95m RMS 413.537m |
| Is1 | AVG 628.192m MIN -5.05725u MAX 2.29898 RMS 1.05538 |
| Is2 | AVG 627.336m MIN -5.05727u MAX 2.29673 RMS 1.05415 |
| VLOAD | AVG 24.0969 MIN 24.0845 MAX 24.1074 RMS 24.0969 |
| VSRC | AVG 379.992 MIN 379.941 MAX 380.053 RMS 379.992 |
| VSW | AVG 189.992 MIN -724.425m MAX 380.776 RMS 268.251 |
| Vs | AVG -25.0132m MIN -24.933 MAX 24.8412 RMS 24.7871 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1074) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0845) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (27.3682) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (53.811) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac5_314.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop5_280.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop5_270.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop5_261.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop5_275.sxgph |
| Other SXGPH Files | |
| default#303#pop | simplis_pop5_303.sxgph |
| Modulator#pop | simplis_pop5_308.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac5_321.sxgph |
