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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|30% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|30% Load |
| Date / Time | 2/7/2015 10:35:53 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\30% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.9146% |
| Frequency(CLK) | 87.506471kHertz |
| Power(LOAD) | 36.3028 |
| Power(SRC) | 37.8491 |
| eta_nom | 95.9146% |
| gain_crossover_freq | 4.76088k |
| gain_margin | 27.1025 |
| gmargin_nom | 27.1025 |
| gxover_nom | 4.76088k |
| iload_nom | 1.50653 |
| min_phase | 49.0124 |
| phase_crossover_freq | 33.0239k |
| min_phase_freq | 4.76088k |
| phase_margin | 48.8263 |
| pmargin_nom | 48.8263 |
| sw_freq_nom | 87.506471kHertz |
| ICout | AVG 4.80189u MIN -1.5056 MAX 1.15401 RMS 905.356m |
| IDQ1 | AVG 99.6276m MIN -530.275m MAX 614.535m RMS 306.304m |
| IDQ2 | AVG 99.5896m MIN -533.337m MAX 614.634m RMS 306.29m |
| ILOAD | AVG 1.50653 MIN 1.50559 MAX 1.50726 RMS 1.50653 |
| ISRC | AVG 99.6276m MIN -530.275m MAX 614.535m RMS 306.304m |
| Im | AVG -102.307u MIN -532.88m MAX 532.671m RMS 308.115m |
| Ip | AVG 140.305u MIN -354.478m MAX 354.838m RMS 234.393m |
| Ir | AVG 37.9981u MIN -614.63m MAX 614.531m RMS 434.405m |
| Is1 | AVG 753.794m MIN -5.06003u MAX 2.66128 RMS 1.24381 |
| Is2 | AVG 752.742m MIN -5.06005u MAX 2.65858 RMS 1.2423 |
| VLOAD | AVG 24.0969 MIN 24.082 MAX 24.1085 RMS 24.0969 |
| VSRC | AVG 379.99 MIN 379.939 MAX 380.053 RMS 379.99 |
| VSW | AVG 189.99 MIN -724.528m MAX 380.776 RMS 268.235 |
| Vs | AVG -30.0733m MIN -24.9588 MAX 24.8526 RMS 24.8195 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1085) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.082) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (27.1025) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (48.8263) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac6_379.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop6_345.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop6_335.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop6_326.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop6_340.sxgph |
| Other SXGPH Files | |
| default#368#pop | simplis_pop6_368.sxgph |
| Modulator#pop | simplis_pop6_373.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac6_386.sxgph |
