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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|35% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|35% Load |
| Date / Time | 2/7/2015 10:36:07 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\35% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.9178% |
| Frequency(CLK) | 87.326516kHertz |
| Power(LOAD) | 42.3512 |
| Power(SRC) | 44.1537 |
| eta_nom | 95.9178% |
| gain_crossover_freq | 4.78929k |
| gain_margin | 26.3038 |
| gmargin_nom | 26.3038 |
| gxover_nom | 4.78929k |
| iload_nom | 1.75754 |
| min_phase | 48.0547 |
| phase_crossover_freq | 30.8916k |
| min_phase_freq | 4.78929k |
| phase_margin | 47.8355 |
| pmargin_nom | 47.8355 |
| sw_freq_nom | 87.326516kHertz |
| ICout | AVG 4.8005u MIN -1.75626 MAX 1.26432 RMS 1.00444 |
| IDQ1 | AVG 116.221m MIN -532.753m MAX 644.276m RMS 321.681m |
| IDQ2 | AVG 116.183m MIN -531.491m MAX 644.357m RMS 321.665m |
| ILOAD | AVG 1.75754 MIN 1.75626 MAX 1.75847 RMS 1.75754 |
| ISRC | AVG 116.221m MIN -532.753m MAX 644.276m RMS 321.681m |
| Im | AVG -104.64u MIN -534.433m MAX 534.221m RMS 308.939m |
| Ip | AVG 142.638u MIN -402.669m MAX 403.04m RMS 269.959m |
| Ir | AVG 37.9977u MIN -644.354m MAX 644.273m RMS 456.096m |
| Is1 | AVG 879.306m MIN -5.0628u MAX 3.0228 RMS 1.43245 |
| Is2 | AVG 878.236m MIN -5.06282u MAX 3.02001 RMS 1.4309 |
| VLOAD | AVG 24.0969 MIN 24.0795 MAX 24.1096 RMS 24.0969 |
| VSRC | AVG 379.988 MIN 379.936 MAX 380.053 RMS 379.988 |
| VSW | AVG 189.989 MIN -724.533m MAX 380.777 RMS 268.217 |
| Vs | AVG -35.3031m MIN -24.9846 MAX 24.8639 RMS 24.8384 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1096) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0795) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (26.3038) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (47.8355) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac7_444.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop7_410.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop7_400.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop7_391.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop7_405.sxgph |
| Other SXGPH Files | |
| default#433#pop | simplis_pop7_433.sxgph |
| Modulator#pop | simplis_pop7_438.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac7_451.sxgph |
