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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|5% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|5% Load |
| Date / Time | 2/7/2015 10:34:47 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\5% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 94.0564% |
| Frequency(CLK) | 90.46684kHertz |
| Power(LOAD) | 6.06027 |
| Power(SRC) | 6.44323 |
| eta_nom | 94.0564% |
| gain_crossover_freq | 445.573 |
| gain_margin | 30.9799 |
| gmargin_nom | 30.9799 |
| gxover_nom | 445.573 |
| iload_nom | 251.495m |
| min_phase | 97.3623 |
| phase_crossover_freq | 44.134k |
| min_phase_freq | 91.7776 |
| phase_margin | 113.117 |
| pmargin_nom | 113.117 |
| sw_freq_nom | 90.46684kHertz |
| ICout | AVG 4.81756u MIN -251.473m MAX 390.691m RMS 247.641m |
| IDQ1 | AVG 16.9687m MIN -502.43m MAX 526.676m RMS 220.696m |
| IDQ2 | AVG 16.9307m MIN -507.269m MAX 525.553m RMS 220.7m |
| ILOAD | AVG 251.495m MIN 251.467m MAX 251.539m RMS 251.495m |
| ISRC | AVG 16.9687m MIN -502.43m MAX 526.676m RMS 220.696m |
| Im | AVG 24.7595u MIN -498.362m MAX 498.374m RMS 294.649m |
| Ip | AVG 13.2402u MIN -85.5853m MAX 85.632m RMS 47.0644m |
| Ir | AVG 37.9996u MIN -498.362m MAX 498.374m RMS 313.751m |
| Is1 | AVG 125.8m MIN -5.04425u MAX 642.235m RMS 249.678m |
| Is2 | AVG 125.7m MIN -5.04425u MAX 641.885m RMS 249.511m |
| VLOAD | AVG 24.097 MIN 24.0944 MAX 24.1009 RMS 24.097 |
| VSRC | AVG 379.998 MIN 379.947 MAX 380.05 RMS 379.998 |
| VSW | AVG 189.998 MIN -722.154m MAX 380.771 RMS 268.297 |
| Vs | AVG -5.0382m MIN -24.8134 MAX 24.7877 RMS 24.0689 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1009) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0944) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (30.9799) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (113.117) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac1_54.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop1_20.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop1_10.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop1_1.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop1_15.sxgph |
| Other SXGPH Files | |
| default#43#pop | simplis_pop1_43.sxgph |
| Modulator#pop | simplis_pop1_48.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac1_61.sxgph |
