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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|50% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|50% Load |
| Date / Time | 2/7/2015 10:36:32 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\50% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.8115% |
| Frequency(CLK) | 86.810059kHertz |
| Power(LOAD) | 60.4964 |
| Power(SRC) | 63.1411 |
| eta_nom | 95.8115% |
| gain_crossover_freq | 4.83828k |
| gain_margin | 23.6665 |
| gmargin_nom | 23.6665 |
| gxover_nom | 4.83828k |
| iload_nom | 2.51056 |
| min_phase | 45.8063 |
| phase_crossover_freq | 25.2744k |
| min_phase_freq | 4.83828k |
| phase_margin | 45.5353 |
| pmargin_nom | 45.5353 |
| sw_freq_nom | 86.810059kHertz |
| ICout | AVG 4.79733u MIN -2.50795 MAX 1.62008 RMS 1.31936 |
| IDQ1 | AVG 166.198m MIN -533.651m MAX 746.728m RMS 374.24m |
| IDQ2 | AVG 166.16m MIN -534.308m MAX 746.767m RMS 374.216m |
| ILOAD | AVG 2.51056 MIN 2.50795 MAX 2.51226 RMS 2.51056 |
| ISRC | AVG 166.198m MIN -533.651m MAX 746.728m RMS 374.24m |
| Im | AVG -109.819u MIN -538.627m MAX 538.406m RMS 311.348m |
| Ip | AVG 147.815u MIN -550.582m MAX 550.98m RMS 378.238m |
| Ir | AVG 37.9967u MIN -746.763m MAX 746.724m RMS 530.264m |
| Is1 | AVG 1.25583 MIN -5.07133u MAX 4.13234 RMS 2.00673 |
| Is2 | AVG 1.25473 MIN -5.07136u MAX 4.12936 RMS 2.00508 |
| VLOAD | AVG 24.0968 MIN 24.0719 MAX 24.1131 RMS 24.0968 |
| VSRC | AVG 379.983 MIN 379.925 MAX 380.053 RMS 379.983 |
| VSW | AVG 189.984 MIN -724.472m MAX 380.777 RMS 268.163 |
| Vs | AVG -50.1828m MIN -25.0639 MAX 24.8988 RMS 24.8832 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1131) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0719) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (23.6665) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (45.5353) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac9_574.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop9_540.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop9_530.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop9_521.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop9_535.sxgph |
| Other SXGPH Files | |
| default#563#pop | simplis_pop9_563.sxgph |
| Modulator#pop | simplis_pop9_568.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac9_581.sxgph |
