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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|60% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|60% Load |
| Date / Time | 2/7/2015 10:36:46 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\60% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.6991% |
| Frequency(CLK) | 86.495464kHertz |
| Power(LOAD) | 72.5901 |
| Power(SRC) | 75.8525 |
| eta_nom | 95.6991% |
| gain_crossover_freq | 4.89133k |
| gain_margin | 21.776 |
| gmargin_nom | 21.776 |
| gxover_nom | 4.89133k |
| iload_nom | 3.0125 |
| min_phase | 43.0874 |
| phase_crossover_freq | 22.0379k |
| min_phase_freq | 4.89133k |
| phase_margin | 42.774 |
| pmargin_nom | 42.774 |
| sw_freq_nom | 86.495464kHertz |
| ICout | AVG 4.7963u MIN -3.00875 MAX 1.87375 RMS 1.54081 |
| IDQ1 | AVG 199.657m MIN -537.479m MAX 824.121m RMS 413.528m |
| IDQ2 | AVG 199.619m MIN -537.409m MAX 824.137m RMS 413.499m |
| ILOAD | AVG 3.0125 MIN 3.00875 MAX 3.01486 RMS 3.0125 |
| ISRC | AVG 199.657m MIN -537.479m MAX 824.121m RMS 413.528m |
| Im | AVG -112.703u MIN -541.11m MAX 540.884m RMS 312.828m |
| Ip | AVG 150.699u MIN -651.406m MAX 651.816m RMS 451.276m |
| Ir | AVG 37.9961u MIN -824.133m MAX 824.117m RMS 585.727m |
| Is1 | AVG 1.50682 MIN -5.07613u MAX 4.88861 RMS 2.39409 |
| Is2 | AVG 1.50569 MIN -5.07615u MAX 4.88554 RMS 2.39241 |
| VLOAD | AVG 24.0963 MIN 24.0664 MAX 24.115 RMS 24.0963 |
| VSRC | AVG 379.98 MIN 379.918 MAX 380.054 RMS 379.98 |
| VSW | AVG 189.98 MIN -724.389m MAX 380.776 RMS 268.124 |
| Vs | AVG -60.2276m MIN -25.1084 MAX 24.9131 RMS 24.907 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.115) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0664) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (21.776) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (42.774) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac10_639.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop10_605.sxgph |
 SRC
ISRC
VSRC
|
|
| SXGPH File | simplis_pop10_595.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop10_586.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop10_600.sxgph |
| Other SXGPH Files | |
| default#628#pop | simplis_pop10_628.sxgph |
| Modulator#pop | simplis_pop10_633.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac10_646.sxgph |
