back to overview ▲
» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|70% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|70% Load |
| Date / Time | 2/7/2015 10:36:59 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\70% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.5852% |
| Frequency(CLK) | 86.223788kHertz |
| Power(LOAD) | 84.6758 |
| Power(SRC) | 88.5867 |
| eta_nom | 95.5852% |
| gain_crossover_freq | 4.9051k |
| gain_margin | 20.1294 |
| gmargin_nom | 20.1294 |
| gxover_nom | 4.9051k |
| iload_nom | 3.51428 |
| min_phase | 42.0352 |
| phase_crossover_freq | 19.5696k |
| min_phase_freq | 4.9051k |
| phase_margin | 41.6959 |
| pmargin_nom | 41.6959 |
| sw_freq_nom | 86.223788kHertz |
| ICout | AVG 4.79541u MIN -3.50918 MAX 2.13654 RMS 1.76851 |
| IDQ1 | AVG 233.177m MIN -535.977m MAX 907.075m RMS 455.321m |
| IDQ2 | AVG 233.139m MIN -536.351m MAX 907.074m RMS 455.289m |
| ILOAD | AVG 3.51428 MIN 3.50917 MAX 3.51742 RMS 3.51429 |
| ISRC | AVG 233.177m MIN -535.977m MAX 907.075m RMS 455.321m |
| Im | AVG -114.959u MIN -543.218m MAX 542.987m RMS 314.089m |
| Ip | AVG 152.954u MIN -753.442m MAX 753.863m RMS 524.715m |
| Ir | AVG 37.9954u MIN -907.071m MAX 907.071m RMS 644.744m |
| Is1 | AVG 1.75772 MIN -5.08014u MAX 5.65396 RMS 2.78358 |
| Is2 | AVG 1.75657 MIN -5.08016u MAX 5.65081 RMS 2.78186 |
| VLOAD | AVG 24.0947 MIN 24.0598 MAX 24.1161 RMS 24.0947 |
| VSRC | AVG 379.977 MIN 379.909 MAX 380.054 RMS 379.977 |
| VSW | AVG 189.977 MIN -724.268m MAX 380.776 RMS 268.085 |
| Vs | AVG -70.1257m MIN -25.1462 MAX 24.9202 RMS 24.9253 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1161) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0598) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (20.1294) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (41.6959) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac11_704.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop11_670.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop11_660.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop11_651.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop11_665.sxgph |
| Other SXGPH Files | |
| DVM Bode Plot Input#log#ac | simplis_ac11_711.sxgph |
| default#693#pop | simplis_pop11_693.sxgph |
| Modulator#pop | simplis_pop11_698.sxgph |
