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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|80% Load
| Test Details | |
| Schematic | 8.2_LLCClosed Loop.sxsch |
| Test | Efficiency and Loop Characterization|Vin Nominal|80% Load |
| Date / Time | 2/7/2015 10:37:12 AM |
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\80% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 95.4650% |
| Frequency(CLK) | 85.975646kHertz |
| Power(LOAD) | 96.7481 |
| Power(SRC) | 101.344 |
| eta_nom | 95.4650% |
| gain_crossover_freq | 4.8918k |
| gain_margin | 18.7152 |
| gmargin_nom | 18.7152 |
| gxover_nom | 4.8918k |
| iload_nom | 4.01579 |
| min_phase | 41.8679 |
| phase_crossover_freq | 17.6787k |
| min_phase_freq | 4.8918k |
| phase_margin | 41.5114 |
| pmargin_nom | 41.5114 |
| sw_freq_nom | 85.975646kHertz |
| ICout | AVG 4.79472u MIN -4.00912 MAX 2.40691 RMS 2.00152 |
| IDQ1 | AVG 266.761m MIN -539.247m MAX 994.216m RMS 499.056m |
| IDQ2 | AVG 266.723m MIN -536.152m MAX 994.204m RMS 499.021m |
| ILOAD | AVG 4.01579 MIN 4.00911 MAX 4.01983 RMS 4.01579 |
| ISRC | AVG 266.761m MIN -539.247m MAX 994.216m RMS 499.056m |
| Im | AVG -116.608u MIN -545.111m MAX 544.876m RMS 315.231m |
| Ip | AVG 154.602u MIN -856.47m MAX 856.899m RMS 598.46m |
| Ir | AVG 37.9947u MIN -994.2m MAX 994.213m RMS 706.517m |
| Is1 | AVG 2.00848 MIN -5.08394u MAX 6.42673 RMS 3.17468 |
| Is2 | AVG 2.00732 MIN -5.08397u MAX 6.42352 RMS 3.17294 |
| VLOAD | AVG 24.0919 MIN 24.052 MAX 24.116 RMS 24.0919 |
| VSRC | AVG 379.973 MIN 379.901 MAX 380.054 RMS 379.973 |
| VSW | AVG 189.974 MIN -724.12m MAX 380.776 RMS 268.044 |
| Vs | AVG -80.2974m MIN -25.1832 MAX 24.9263 RMS 24.9403 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.116) is less than or equal to Max. Output1 Voltage Spec (25.2) |
| Min_VLOAD | PASS: Min. Output1 Voltage (24.052) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
| min_gain_margin | PASS: Gain Margin (18.7152) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (41.5114) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac12_769.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop12_735.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop12_725.sxgph |
 Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
| SXGPH File | simplis_pop12_716.sxgph |
 Secondary
CLK
ICout
Is1
Is2
Vs
|
|
| SXGPH File | simplis_pop12_730.sxgph |
| Other SXGPH Files | |
| default#758#pop | simplis_pop12_758.sxgph |
| Modulator#pop | simplis_pop12_763.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac12_776.sxgph |
