back to overview ▲

» DVM Test Report: VOUT=1.505V|Bode Plot|Vin Nominal|Light Load

Test Details
Schematic 6.3_LTC3406B- DVM ADVANCED.sxsch
Test VOUT=1.505V|Bode Plot|Vin Nominal|Light Load
Date / Time 2/7/2015 10:26:24 AM
Report Directory promote_graphs\VOUT=1.505V\BodePlot\Vin Nominal\Light Load
Log File report.txt
Screenshot schematic.png
Status FAIL
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 91.1062%
Frequency(CLK) 955.70284kHertz
Power(LOAD) 75.3225m
Power(SRC) 82.6755m
gain_crossover_freq 13.4247k
gain_crossover_freq_nom 13.4247k
gain_margin 49.9661
gain_margin_nom 49.9661
min_phase 11.5623
phase_crossover_freq 642.362k
min_phase_freq 6.30957k
phase_margin 14.8135
phase_margin_nom 14.8135
ILOAD
AVG
50.0255m
MIN
49.9785m
MAX
50.0675m
RMS
50.0255m
ILOUT
AVG
50.0255m
MIN
-142.604u
MAX
251.149m
RMS
91.3536m
ISRC
AVG
16.5357m
MIN
287.388u
MAX
500.173m
RMS
52.2926m
SW
AVG
1.51121
MIN
-800.457m
MAX
5.70005
RMS
2.10859
VLOAD
AVG
1.50568
MIN
1.50427
MAX
1.50695
RMS
1.50568
VOUT
AVG
1.50568
MIN
1.50427
MAX
1.50695
RMS
1.50568
VSRC
AVG
4.99998
MIN
4.9995
MAX
5
RMS
4.99998
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.50695) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.50427) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
min_gain_margin PASS: Gain Margin (49.9661) is greater than Min. Gain Margin (12)
min_phase_margin FAIL: Phase Margin (14.8135) is not greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac1_36.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop1_19.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop1_9.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop1_14.sxgph
Other SXGPH Files
clock#pop simplis_pop1_1.sxgph
DVM Bode Plot Input#log#ac simplis_ac1_43.sxgph