| Test Details | |
| Schematic | 6.3_LTC3406B- DVM ADVANCED.sxsch |
| Test | Pre-Process |
| Date / Time | 2/9/2015 5:36:53 PM |
| Report Directory | scripting\Pre-Process |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | PASS |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Frequency(CLK) | 955.63308kHertz |
| GAIN | MIN -61.6648 MAX 30.3333 |
| ILOAD | MIN 1.49635 MAX 1.50441 |
| ILOUT | MIN 1.11755 MAX 1.89 |
| ISRC | MIN 466.041u MAX 1.89047 |
| PHASE | MIN -168.703 MAX 86.7445 |
| SW | MIN -1.456 MAX 5.05159 |
| VLOAD | MIN 1.50133 MAX 1.50942 |
| VOUT | MIN 1.50133 MAX 1.50942 |
| VSRC | MIN 5.49811 MAX 5.5 |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (1.50942) is less than or equal to Max. Output1 Voltage Spec (1.58025) |
| Min_VLOAD | PASS: Min. Output1 Voltage (1.50133) is greater than or equal to Min. Output1 Voltage Spec (1.42975) |
![]() LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop1_19.sxgph |
![]() Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac1_36.sxgph |
![]() SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop1_9.sxgph |
![]() default
CLK
ILOUT
SW
VOUT
|
|
| SXGPH File | simplis_pop1_14.sxgph |
| Other SXGPH Files | |
| clock#pop | simplis_pop1_1.sxgph |
| DVM Bode Plot Input#log#ac | simplis_ac1_43.sxgph |