SystemDesigner

SystemDesigner Gain

The SystemDesigner Gain models an amplification of a bus value. The Gain can be any integer greater than 1.

The propagation delay can be defined as a fixed time, as asynchronous to any clock, or as a synchronous delay where the delay is a number of SystemDesigner-clocks cycles. In this release of SystemDesigner, the synchronous delay is supported only for integer-sampled data simulations.

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Model Name:

SystemDesigner Gain

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector
Menu Location:

SystemDesigner Functions (max. 32 bit)

Symbol Library:

SIMPLIS_SystemDesigner.sxslb

Model File:

SIMPLIS_SystemDesigner.lb

Subcircuit Name:

SIMPLIS_SD_GAIN_32

Symbols:

Multiple Selections:

Only one device at a time can be edited.

Editing the Gain

To configure the Gain, double click the symbol to open the parameter editing dialog.

Label Parameter Description

Gain

The gain constant. The gain can be any signed 32 bit integer.

Use asynchronous delay

Implements a combinatorial model where the output voltage changes in response to the input voltage(s) change after a propagation delay.

Propagation Delay

The propagation delay from an input change to an output change in seconds.
This parameter is used only in models with Asynchronous delay.

Use synchronous delay

In response to an input voltage change, the output voltage changes after a designated number of clock cycles.

Delay

The propagation delay from an input change to an output change in number of clock cycles. The output will not change until the number of clock cycles has been reached. The output will then change state only on the selected Clock source edges specified by Trigger edge.
The Clock source can be set using the SystemDesigner->Edit SystemDesigner Clocks... menu item.
This parameter is used only in models with Synchronous delay.

Clock source

Specifies the global clock used for the Synchronous delay block.
The Clock source can be set using the SystemDesigner->Edit SystemDesigner Clocks... menu item.
This parameter is used only in models with Synchronous delay.

Trigger edge

Sets the output to change on specific edges of the Clock source :

  • 0_TO_1 The output changes only on rising edges of the Clock source
  • 1_TO_0 The output changes only on falling edges of the Clock source
This parameter is used only in models with Synchronous delay.

Use 32 bit signed

The full 32-bit signed data is output.

Limit output to:

The output is limited to a Signed or Unsigned number with a designated number of bits.

Number type

The output will be limited to either a Signed or Unsigned number if Limit output to is selected.

  • Signed numbers include integers from -2Number of bits-1 to 2Number of bits-1-1
  • Unsigned numbers include integers from 0 to 2Number of bits
This parameter is used only in models with Limit output to selected.

Number of bits

The limit on the output depends on the Number type parameter :

  • Signed numbers include integers from -2Number of bits-1 to 2Number of bits-1-1
  • Unsigned numbers include integers from 0 to 2Number of bits
This parameter is used only in models with Limit output to selected.

Initial Condition

Initial condition of the output at time=0. Value is the output bus represented in decimal format.

Examples

The SystemDesigner Gain is used in numerous examples:

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