SIMPLIS Reference: Advanced Digital Component Reference

Introduction
General Behaviour
- Intertial Delay
- Transport Delay
- Flip-Flop Delay Parameters
- Flip-Flop Minimum Clock Width
- Discrete Filters
Parts Available Summary
- Flip-Flops
- Gates
- Arithmetic
- A to D / D to A
- Sources
- Functions
- Counters
- Latches
- Discrete Filters
- Registers
D-Type Flip-Flop
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Input Resistance
- Output Resistance
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
D-Type Flip-Flop w/ SET/RST
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set/Reset Type
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
S/R Flip-Flop
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Input Resistance
- Output Resistance
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
S/R Flip-Flop w/ SET/RST
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set/Reset Type
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
J/K Flip-Flop
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Input Resistance
- Output Resistance
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
J/K Flip-Flop w/ SET/RST
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set/Reset Type
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Toggle Flip-Flop
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Input Resistance
- Output Resistance
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Toggle Flip-Flop w/ SET/RST
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set/Reset Type
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
AND Gate
- Delay
- Hysteresis
- Initial Condition
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
NAND Gate
- Delay
- Hysteresis
- Initial Condition
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
OR Gate
- Delay
- Hysteresis
- Initial Condition
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
NOR Gate
- Delay
- Hysteresis
- Initial Condition
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Exclusive-OR Gate
- Delay
- Hysteresis
- Initial Condition
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Comparator
- Delay
- Hysteresis
- Initial Condition
- Input Resistance
- Output Resistance
- Output High Voltage
- Output Low Voltage
Buffer
- Delay
- Hysteresis
- Initial Condition
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Inverter
- Delay
- Hysteresis
- Initial Condition
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Adder
- Code
- Ground Ref
- Hysteresis
- Initial Condition
- Initial Condition of Overflow
- Num. Bits
- Output Delay
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Subtracter
- Code
- Ground Ref
- Hysteresis
- Initial Condition
- Initial Condition of Overflow
- Num. Bits
- Output Delay
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Multiplier
- Code
- Ground Ref
- Hysteresis
- Initial Condition
- Num. Bits A
- Num. Bits B
- Output Delay
- Input Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Divider
- Code
- Ground Ref
- Hysteresis
- Initial Condition
- Initial Condition of Overflow
- Initial Condition of Remainder
- Num. Bits A
- Num. Bits B
- Output Delay
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Fixed Point Divider
- Code
- Ground Ref
- Hysteresis
- Initial Condition
- Initial Condition of Overflow
- Num. Bits A
- Num. Bits B
- Num. Bits C
- Output Delay
- Radix Position A
- Radix Position B
- Radix Position C
- Input Resistance
- Round Mode
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Analog to Digital Converter - Operation
- Conversion Timing
Analog to Digital Converter - Parameters
- Code
- Convert Time
- Data ready delay
- Enable Delay
- Initial Condition
- Initial Condition of Data Ready
- Initial Condition of Overflow
- Minimum Clk Width
- Num. Bits
- Offset
- Range
- Input Resistance
- Output Resistance
- Sample delay
- Threshold
- Output High Voltage
- Output Low Voltage
Analog to Digital Converter w/ Adjustable Voltage Reference - Operation
- Input Range and Offset:
Analog to Digital Converter w/ Adjustable Voltage Reference - Parameters
- Code
- Convert Time
- Data ready delay
- Enable Delay
- Hysteresis
- Initial Condition
- Initial Condition of Data Ready
- Initial Condition of Overflow
- Minimum Clk Width
- Num. Bits
- Input Resistance
- Output Resistance
- Sample delay
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Digital to Analog Converter (Non-clocked)
- Code
- Hysteresis
- Initial Condition
- Num. Bits
- Delay
- Offset
- Range
- Input Resistance
- Output Resistance
- Threshold
Digital Pulse Source
- Start Delay
- Ground Ref
- Period (0 for single pulse)
- Output Resistance
- Output High Voltage
- Output Low Voltage
- Pulse Width
Digital Signal Source
- Ground Ref
- Num. Bits
- Redefine Source?
- Output Resistance
- Source Definition
- Output High Voltage
- Output Low Voltage
Asymmetric Delay
- Fall Delay
- Ground Ref
- Hysteresis
- Initial Condition
- Input Resistance
- Rise Delay
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Digital Comparator
- Code
- Ground Ref
- Hysteresis
- Initial Condition
- Num. Bits
- Output Delay
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Digital Constant
- Format
- Num. Bits
- Value
Digital Lookup Table
- Default Value
- Initial Condition
- Num. Bits In
- Num. Bits Out
- Output Delay
- Redefine Table?
- Source Definition
Digital Lookup Table allowing Don't Care in Input Definition
- Default Value
- Initial Condition
- Num. Bits In
- Num. Bits Out
- Output Delay
- Redefine Table?
Digital Mux
- Ground Ref
- Hysteresis
- Initial Condition
- Inversion?
- Number of Bits per Input
- Number of Inputs
- Delay
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Digital Demux
- Ground Ref
- Hysteresis
- Initial Condition
- Inactive Level
- Inversion?
- Number of Bits per Output
- Number of Outputs
- Delay
- Input Resistance
- Output Resistance
- Threshold
- Output High Voltage
- Output Low Voltage
Up Counter
- Clk to Output Delay
- Enable Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Num. Bits
- Reset delay
- Reset Level
- Reset Type
- Input Resistance
- Output Resistance
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Down Counter
- Clk to Output Delay
- Enable Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Num. Bits
- Input Resistance
- Output Resistance
- Set delay
- Set Level
- Set Type
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Up/Down Counter
- Clk to Output Delay
- Enable Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Minimum Clk Width
- Num. Bits
- Reset To
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set/Reset Type
- Set To
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
D-Type Latch
- Ground Ref
- Hysteresis
- Initial Condition
- Delay
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Threshold
- Output High Voltage
- Output Low Voltage
S/R Latch
- S/R Dominance
- Enable
- Ground Ref
- Hysteresis
- Initial Condition
- Delay
- Input Resistance
- Output Resistance
- Set/Reset Level
- Threshold
- Output High Voltage
- Output Low Voltage
S/R Latch w/ Enable
- S/R Dominance
- Enable
- Ground Ref
- Hysteresis
- Initial Condition
- Delay
- Input Resistance
- Output Resistance
- Set/Reset Level
- Threshold
- Output High Voltage
- Output Low Voltage
Data Register
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Load Level
- Minimum Clk Width
- Num. Bits
- Reset To (Async)
- Reset To (Sync)
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set To (Async)
- Set To (Sync)
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Shift Register
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Left/Right_Level
- Load/Shift Level
- Minimum Clk Width
- Num. Bits
- Reset To (Async)
- Reset To (Sync)
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set To (Async)
- Set To (Sync)
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Shift Register (Left)
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Load/Shift Level
- Minimum Clk Width
- Num. Bits
- Reset To (Async)
- Reset To (Sync)
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set To (Async)
- Set To (Sync)
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Shift Register (Right)
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Load/Shift Level
- Minimum Clk Width
- Num. Bits
- Reset To (Async)
- Reset To (Sync)
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set To (Async)
- Set To (Sync)
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Shift Register (Multi-bit)
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Left/Right_Level
- Load/Shift Level
- Minimum Clk Width
- Num. Bits
- Reset To (Async)
- Reset To (Sync)
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set To (Async)
- Set To (Sync)
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
Barrel Shifter
- Clk to Output Delay
- Ground Ref
- Hold Time
- Hysteresis
- Initial Condition
- Left/Right_Level
- Load/Shift Level
- Minimum Clk Width
- Num. Bits
- Reset To (Async)
- Reset To (Sync)
- Input Resistance
- Output Resistance
- Set/Reset Delay
- Set/Reset Level
- Set To (Async)
- Set To (Sync)
- Setup Time
- Threshold
- Trigger Condition
- Output High Voltage
- Output Low Voltage
1-Pole Discrete Filter - Operation
1-Pole Discrete Filter - Parameters
- D0
- Initial Condition
- N0
- N1
- Acquisition Time in seconds
2-Pole Discrete Filter - Operation
2-Pole Discrete Filter - Parameters
- D0
- D1
- Initial Condition
- N0
- N1
- N2
- Acquisition Time in seconds
PID Discrete Filter - Operation
PID Discrete Filter - Parameters
- Derivative Method
- Pole Factor
- Initial Condition
- Integration Method
- KD
- KI
- KP
- Acquisition Time in sec.

Introduction

This section describes the various components available and how to use them in the SIMetrix schematic environment.

General Behaviour

Intertial Delay

Any Input to Output delay for the new Advanced Digital components incorporates inertial delay where, if the pulse width of the incoming signal is less than the Input to Output delay of a particular device, then there is no resulting change in the output. In the example below, one of the input pulses is narrower than the input-to-output delay of a buffer logic gate. In that instance, the output of the buffer gate effectively "ignores" that one input pulse.

This inertial delay behavior describes the Delay parameter for all the Advanced Digital Logic Gates as well as the Out Delay of the Adder, Subtracter, Multiplier, Comparator and Latches and each of the delay parameters of the Analog-to-Digital Converters, Counters and Flip Flops.

None of the delay parameters of the SIMPLIS Advanced Digital components may be set to zero.

Transport Delay

By contrast, the Classic SIMPLIS digital gates model transport delay, in which they are able to respond to any width signal at their input and reproduce that same width signal at the output after the specified delay interval.

Flip-Flop Delay Parameters

This example shows an edge triggered D-type flip flop with asynchronous set and reset. In this example, Set and Reset are selected to be active high. The following diagram shows the definition of the Clk to Output Delay as well as the Set/Reset Delay. All Flip Flop devices have a Clk to Output Delay parameter and all Flip Flops with the Set and Reset feature have a Set/Reset Delay.

Flip-Flop Minimum Clock Width

As in this example of a D-type flip flop, where the device is set to trigger on the positive going edge of the clock, if the width of the clock pulse is narrower than the specified Minimum Clock Width, the clock pulse is ignored.

Discrete Filters

Each of these discrete filters is driven by an input clock signal. For proper operation, the input clock signal needs to be made up of a train of pulses with pulse widths equal to or wider than the "Time of Acquisition" set for the filter. For the most efficient simulation, this kind of pulses can be generated by driving periodic pulses through the "Sampling Clock Generator for Discrete Filters". If the "Sampling Clock Generator for Discrete Filters" is used to generate the input clock signals for the discrete filters, the driving periodic pulses can have pulse widths shorter than the time of acquisition as long as they are well defined pulses

If the time of acquisition is $\text{t}_{\text{ACQ}}$, then the "Sampling Clock Generator for Discrete Filters" will generate a pulse whose pulse width is equal to $\text{t}_{\text{ACQ}}$ every time its "TRIG" input makes a positive transition exceeding 3V. During this pulse, the discrete filter will sample the input data at the "IN" input pin and it will take $\text{t}_{\text{ACQ}}$ for it to satisfactorily acquire the input data. After $\text{t}_{\text{ACQ}}$ has expired, the discrete filter will update its output, and the output will settle within a time duration less than or equal to $\text{t}_{\text{ACQ}}$. In addition, during this duration when the output is updated, the output "CLK_OUT" is raised to a high value.

A discrete filter with more than two poles can be synthesized through a cascade of one-pole and/or two-pole discrete filters. In such case, the timing signal for each driven stage is derived from the "CLK_OUT" signal of the immediately preceding stage.

Parts Available Summary

Flip-Flops

Gates

Arithmetic

A to D / D to A

Sources

Functions

Counters

Latches

Discrete Filters

Registers

D-Type Flip-Flop

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Input Resistance

Output Resistance

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

D-Type Flip-Flop w/ SET/RST

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set/Reset Type

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

S/R Flip-Flop

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Input Resistance

Output Resistance

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

S/R Flip-Flop w/ SET/RST

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set/Reset Type

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

J/K Flip-Flop

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Input Resistance

Output Resistance

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

J/K Flip-Flop w/ SET/RST

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set/Reset Type

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Toggle Flip-Flop

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Input Resistance

Output Resistance

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Toggle Flip-Flop w/ SET/RST

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set/Reset Type

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

AND Gate

Delay

Hysteresis

Initial Condition

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

NAND Gate

Delay

Hysteresis

Initial Condition

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

OR Gate

Delay

Hysteresis

Initial Condition

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

NOR Gate

Delay

Hysteresis

Initial Condition

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Exclusive-OR Gate

Delay

Hysteresis

Initial Condition

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Comparator

Delay

Hysteresis

Initial Condition

Input Resistance

Output Resistance

Output High Voltage

Output Low Voltage

Buffer

Delay

Hysteresis

Initial Condition

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Inverter

Delay

Hysteresis

Initial Condition

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Adder

Code

Ground Ref

Hysteresis

Initial Condition

Initial Condition of Overflow

Num. Bits

Output Delay

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Subtracter

Code

Ground Ref

Hysteresis

Initial Condition

Initial Condition of Overflow

Num. Bits

Output Delay

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Multiplier

Code

Ground Ref

Hysteresis

Initial Condition

Num. Bits A

Num. Bits B

Output Delay

Input Resistance

Threshold

Output High Voltage

Output Low Voltage

Divider

Code

Ground Ref

Hysteresis

Initial Condition

Initial Condition of Overflow

Initial Condition of Remainder

Num. Bits A

Num. Bits B

Output Delay

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Fixed Point Divider

Code

Ground Ref

Hysteresis

Initial Condition

Initial Condition of Overflow

Num. Bits A

Num. Bits B

Num. Bits C

Output Delay

Radix Position A

Radix Position B

Radix Position C

Input Resistance

Round Mode

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Analog to Digital Converter - Operation

This is a 1-32 bit analog to digital converter. The operation of this device is illustrated by the following diagrams:

Conversion Timing

The ADC starts the conversion at the rising or falling edge of the clock, depending on the selected value of the Trigger Condition. The sampling of the analog input signal begins at this point. The sampling of the input is complete after an interval of Sample delay. The output data changes in response to this, Convert Time seconds after the clock trigger event. At the same time that the output initially changes, the Data ready output goes low (inactive) then high again after a delay equal to Data ready delay. It is possible to start a new conversion before the previous conversion is complete provided it is started later than Minimum clock width seconds after the previous conversion was started. Minimum clock width must always be less than Convert Time. If the Minimum clock width specification is violated, the conversion will not start.

Analog to Digital Converter - Parameters

Code

Convert Time

Data ready delay

Enable Delay

Initial Condition

Initial Condition of Data Ready

Initial Condition of Overflow

Minimum Clk Width

Num. Bits

Offset

Range

Input Resistance

Output Resistance

Sample delay

Threshold

Output High Voltage

Output Low Voltage

Analog to Digital Converter w/ Adjustable Voltage Reference - Operation

This is a 1-32 bit analog to digital converter. The operation of this device for the most part identical to the Analog to Digital Converter described above. As shown in this figure , the major difference is that the range and offset of this device is controlled by the voltage on the analog reference pin VREF.

Input Range and Offset:

This ADC has an Analog Reference that determines the Input Voltage Range and the Input Voltage Offset based on the value of the analog voltage present between the VREF and RTN pins. The voltage at the VREF pin must always be positive and greater than zero. The Input Voltage Range is equal to the voltage between the VREF and RTN pins while the Input Voltage Offset is equal to 1/2 of the Input Voltage Range.

Analog to Digital Converter w/ Adjustable Voltage Reference - Parameters

Code

Convert Time

Data ready delay

Enable Delay

Hysteresis

Initial Condition

Initial Condition of Data Ready

Initial Condition of Overflow

Minimum Clk Width

Num. Bits

Input Resistance

Output Resistance

Sample delay

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Digital to Analog Converter (Non-clocked)

Code

Hysteresis

Initial Condition

Num. Bits

Delay

Offset

Range

Input Resistance

Output Resistance

Threshold

Digital Pulse Source

Start Delay

Ground Ref

Period (0 for single pulse)

Output Resistance

Output High Voltage

Output Low Voltage

Pulse Width

Digital Signal Source

Ground Ref

Num. Bits

Redefine Source?

Output Resistance

Source Definition

Output High Voltage

Output Low Voltage

Asymmetric Delay

Fall Delay

Ground Ref

Hysteresis

Initial Condition

Input Resistance

Rise Delay

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Digital Comparator

Code

Ground Ref

Hysteresis

Initial Condition

Num. Bits

Output Delay

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Digital Constant

Format

Num. Bits

Value

Digital Lookup Table

Default Value

Initial Condition

Num. Bits In

Num. Bits Out

Output Delay

Redefine Table?

Source Definition

Digital Lookup Table allowing Don't Care in Input Definition

Default Value

Initial Condition

Num. Bits In

Num. Bits Out

Output Delay

Redefine Table?

Digital Mux

Ground Ref

Hysteresis

Initial Condition

Inversion?

Number of Bits per Input

Number of Inputs

Delay

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Digital Demux

Ground Ref

Hysteresis

Initial Condition

Inactive Level

Inversion?

Number of Bits per Output

Number of Outputs

Delay

Input Resistance

Output Resistance

Threshold

Output High Voltage

Output Low Voltage

Up Counter

Clk to Output Delay

Enable Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Num. Bits

Reset delay

Reset Level

Reset Type

Input Resistance

Output Resistance

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Down Counter

Clk to Output Delay

Enable Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Num. Bits

Input Resistance

Output Resistance

Set delay

Set Level

Set Type

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Up/Down Counter

Clk to Output Delay

Enable Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Minimum Clk Width

Num. Bits

Reset To

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set/Reset Type

Set To

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

D-Type Latch

Ground Ref

Hysteresis

Initial Condition

Delay

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Threshold

Output High Voltage

Output Low Voltage

S/R Latch

S/R Dominance

Enable

Ground Ref

Hysteresis

Initial Condition

Delay

Input Resistance

Output Resistance

Set/Reset Level

Threshold

Output High Voltage

Output Low Voltage

S/R Latch w/ Enable

S/R Dominance

Enable

Ground Ref

Hysteresis

Initial Condition

Delay

Input Resistance

Output Resistance

Set/Reset Level

Threshold

Output High Voltage

Output Low Voltage

Data Register

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Load Level

Minimum Clk Width

Num. Bits

Reset To (Async)

Reset To (Sync)

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set To (Async)

Set To (Sync)

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Shift Register

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Left/Right_Level

Load/Shift Level

Minimum Clk Width

Num. Bits

Reset To (Async)

Reset To (Sync)

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set To (Async)

Set To (Sync)

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Shift Register (Left)

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Load/Shift Level

Minimum Clk Width

Num. Bits

Reset To (Async)

Reset To (Sync)

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set To (Async)

Set To (Sync)

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Shift Register (Right)

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Load/Shift Level

Minimum Clk Width

Num. Bits

Reset To (Async)

Reset To (Sync)

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set To (Async)

Set To (Sync)

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Shift Register (Multi-bit)

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Left/Right_Level

Load/Shift Level

Minimum Clk Width

Num. Bits

Reset To (Async)

Reset To (Sync)

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set To (Async)

Set To (Sync)

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

Barrel Shifter

Clk to Output Delay

Ground Ref

Hold Time

Hysteresis

Initial Condition

Left/Right_Level

Load/Shift Level

Minimum Clk Width

Num. Bits

Reset To (Async)

Reset To (Sync)

Input Resistance

Output Resistance

Set/Reset Delay

Set/Reset Level

Set To (Async)

Set To (Sync)

Setup Time

Threshold

Trigger Condition

Output High Voltage

Output Low Voltage

1-Pole Discrete Filter - Operation

The transfer function in the z-domain from the input I(z) to the output O(z) for the one-pole discrete filter is:

\[ T(z) = \frac{O(z)}{I(z)} = \frac{N1\cdot z + N0}{z + D0} = \frac{N1 + N0\cdot z^{-1}}{1 + D0\cdot z^{-1}} \]

For example, if N1, N0, and D0 have been set to 0, 0.1, and -0.99, respectively, the resulting one-pole discrete filter will have a DC gain of 10.0 and a pole located at 0.99.

The parameters required for the discrete filter can be found in the device documentation below.

1-Pole Discrete Filter - Parameters

Initial Condition

Acquisition Time in seconds

2-Pole Discrete Filter - Operation

\[ T(z) = \frac{N2\cdot z^2 + N1\cdot z + N0}{z^2 + D1\cdot z + D0} = \frac{N2 + N1\cdot z^{-1} + N0\cdot z^{-2}}{1 + D1\cdot z^{-1} + D0\cdot z^{-2}} \]

\[ O(n) + D1\cdot O(n-1) + D0\cdot O(n-2) = N2\cdot I(n) + N1\cdot I(n-1) + N0\cdot I(n-2) \]

The parameters required for the discrete filter can be found in the device documentation.

2-Pole Discrete Filter - Parameters

Initial Condition

Acquisition Time in seconds

PID Discrete Filter - Operation

where the A in the three coefficients $K_{PA}$, $K_{IA}$, and $K_{DA}$ are used to signify that these are the coefficients associated with Eq. (1), which is defined for the analog PID filter.

Since (1) has two zeroes and one pole, there are more zeroes than poles, resulting in an improper transfer function / filter. A pole is sometimes added to the derivative term to limit the bandwidth at higher frequencies. One form for such a PID filter with a pole added for the derivative action is:

\[ T(s) = K_{PA} + \dfrac{K_{IA}}{s} + \dfrac{K_{DA}s}{\gamma K_{DA}s + 1} \tag{2} \]

\[ T(z) = K_P + \frac{K_I}{S_1(z)} + \frac{K_DS_D(z)}{\gamma K_DS_D(z) + 1} \tag{3} \]

where $K_P$, $K_I$, and $K_D$ are coefficients entered by the user. To match the frequency response of the discrete PID filter represented by (3) to the frequency response of the analog PID filter represented by (2), a first-order approximation is to set

\[ K_P = K_{PA} \] \[ K_I = K_{IA}.T_{\text{SAMPLING}} \] \[ K_D = K_{DA}/T_{\text{SAMPLING}} \tag{4} \]

where $T_{\text{SAMPLING}}$ is the sampling period. If this first-order approximation is used, the frequency response for (3) will have a very good match with the frequency response for (2), as long as the poles and zeroes of (3) are more than two decades below the sampling frequency.

The functions $S_I(z)$ and $S_D(z)$ are transfer functions in the z-domain according to the integration and derivative methods selected, respectively. The choices for the method are "Forward-Euler,""Backward-Euler," and "Trapezoidal."

\[ \arrayeqnstretch S_I(z),S_D(z) = \left\{ \begin{array}{ll} z-1 & \text{Forward Euler} \\ \dfrac{z-1}{z} & \text{Backward Euler} \\ \dfrac{2(z-1)}{z+1} & \text{Trapezoidal} \end{array} \right. \tag{5} \]

The integration and the derivative methods are sometimes referred to as the mapping / transformation in the literature. Mapping and transformation are easy and simple ways to generate discrete or digital filters with frequency responses that are approximates of the frequency response of the original s-domain analog filter. The approximation is reasonable if the poles and zeros of the original analog filter are more than two decades below the sampling frequency.

Due to the nature of (3) and (5), the discrete PID filter has two poles in the z-domain, one from the integration term, and one from the derivative term. The pole from the integration term is always located at z=1 and the pole due to the derivative term is located at:

\[ \arrayeqnstretch P_{D,Z} = \left\{ \begin{array}{ll} \dfrac{\gamma K_D-1}{\gamma K_D} & \text{Forward Euler}\\ \dfrac{\gamma K_D}{\gamma K_D + 1} & \text{Backward Euler} \\ \dfrac{\gamma 2\gamma K_D -1}{2\gamma K_D + 1} & \text{Trapeziodal} \end{array} \right. \tag{6} \]

Since the location of this pole should not yield unstable responses, at the very minimum, the restraint on $P_{D,Z}$ is:

\[ \gamma K_D \geq \left\{ \begin{array}{ll} 1 & \text{Forward Euler} \\ 0 & \text{Backward Euler} \\ 0.5 & \text{Trapeziodal} \end{array} \right. \tag{8} \]

Once the value of $P_{D,Z}$ is set, Y can be computed from (6). The corresponding pole location in the s-domain for the pole $P_{D,Z}$ in the z-domain is:

If $P_{D,Z}$ is set to 0.5, the corresponding pole in the s-domain would have a corner frequency of about 0.11 of the sampling frequency.

If there are already extra low-pass filter(s) along the path of feedback, it may be desirable not to introduce the extra pole associated with the derivative term in the discrete PID filter described here. While it is not exactly the same as removing the extra pole, placing $P_{D,Z}$ at $z=0.0$, the center of the origin of the complex plane, has almost the same net effect. Such a pole will have no effect on the magnitude of the derivative term, but it will introduce a phase delay to the derivative term. Such a phase delay is minimal until the signal of interest is at or above one-tenth of the sampling frequency.

If the poles and zeros of the original analog PID filter are well below the sampling frequency, then the three integration methods yield essentially the same result and the three derivative methods yield essentially the same result. The three methods were provided as a convenience if the user is using one of the three mappings or transformations as a quick way to implement a discrete PID filter when the desired analog PID transfer function has been established.

In addition, if one is using one of the three mappings, or transformations, the derivative method should be set to the same as the integration method. The two methods are allowed to be different here in case the user does not come from the point of view of mapping or transformation, but from the point of view of how to implement the integration and how to derive the derivative from the input samples.

The parameters required for the discrete filter can be found in the device documentation following.

Property Name	CLK_TO_OUT_DELAY (see Flip-Flop Delay Parameters).
Data Type	NUMBER
Description	Delay from triggering edge of clock until output changes

Property Name	GNDREF
Data Type	STRING
Options	Y, N
Description	Determines whether or not a device has a ground reference pin

Property Name	HOLD_TIME
Data Type	NUMBER
Description	Minimum time that input data signals must remain constant after triggering clock edge to register as a valid change in input state

Property Name	HYSTWD
Data Type	NUMBER
Description	Hysteretic-window width centered around TH (Threshold voltage)

Property Name	IC
Data Type	NUMBER
Options	0, 1
Description	Initial condition of the flip-flop's output

Property Name	MIN_CLK (see Flip-Flop Delay Parameters).
Data Type	NUMBER
Description	Minimum valid clock width

Property Name	ROUT
Data Type	NUMBER
Description	Output resistance

Property Name	SETUP_TIME
Data Type	NUMBER
Description	Minimum time that input data signals must remain constant before triggering clock edge to register as a valid change in input state

Property Name	TRIG_COND
Data Type	STRING
Options	0_TO_1, 1_TO_0
Description	Determines the triggering condition of the clock pin, either the rising edge or the falling edge

Property Name	MIN_CLK (see Flip-Flop Minimum Clock Width)
Data Type	NUMBER
Description	Minimum valid clock width

Property Name	SET_RESET_DELAY (see Flip-Flop Delay Parameters).
Data Type	NUMBER
Description	Delay from time set / reset pin goes active until output is set / reset

Property Name	SET_RESET_LEVEL
Data Type	INTEGER
Options	0, 1
Description	Determines the set / reset level of a device, 1 means active high, 0 means active low

Property Name	SET_RESET_TYPE
Data Type	STRING
Options	SYNC, ASYNC
Description	Determines whether or not output events are synchronized with a clock event

Property Name	SET_RESET_DELAY (Additional Info)
Data Type	NUMBER
Description	Delay from time set / reset pin goes active until output is set / reset

Property Name	SET_RESET_DELAY ()
Data Type	NUMBER
Description	Delay from time set / reset pin goes active until output is set / reset

Property Name	DELAY (see Inertial Delay).
Data Type	NUMBER
Description	Delay from time an input pin goes active until output changes

Property Name	DELAY (see Intertial Delay).
Data Type	NUMBER
Description	Delay from time an input pin goes active until output changes

Property Name	IC_OFL
Data Type	STRING
Options	POS, NEG, NONE
Description	Initial condition of the overflow outputs of a device, POS means POFL high, NEG means NOFL high, and NONE means both POFL and NOFL are low

Property Name	NUMBITS
Data Type	INTEGER
Description	Number of input or output bits of a device, depending on the device

Property Name	OUT_DELAY
Data Type	NUMBER
Description	Delay from when the input state changes until output changes

Property Name	NUMBITS_A
Data Type	INTEGER
Description	Number of bits for the first input of a multi-input device

Property Name	NUMBITS_B
Data Type	INTEGER
Description	Number of bits for the second input of a multi-input device

Property Name:	CODE
Data Type:	STRING
Options:	UNSIGNED, TWOS_COMPLEMENT, BINARY_OFFSET
Description:	Encoding scheme for binary inputs / outputs for multi-pin I/O

Property Name:	IC_REMAINDER
Data Type:	NUMBER
Description:	Initial condition of the remainder outputs of a divider

Property Name:	NUMBITS_C
Data Type:	INTEGER
Description:	Number of bits for the output of a fixed point divider

Property Name:	RADIX_POS_A
Data Type:	NUMBER
Description:	Radix position for the first input of a fixed point divider

Property Name:	RADIX_POS_B
Data Type:	NUMBER
Description:	Radix position for the second input of a fixed point divider

Property Name:	RADIX_POS_C
Data Type:	NUMBER
Description:	Radix position for the output of a fixed point divider

Property Name:	ROUND_MODE
Data Type:	STRING
Options:	UP, DOWN, CEILING, FLOOR, HALF_UP, HALF_DOWN, HALF_EVEN
Description:	Rounding mode for a digital fixed point divider

Property Name	CONVERT_TIME
Data Type	NUMBER
Description	Time required to convert analog input to digital output

Property Name	DATA_READY_DELAY
Data Type	NUMBER
Description	Delay from time when the output changes until the Data Ready signal is true

Property Name	ENABLE_DELAY
Data Type	NUMBER
Description	Delay from time enable pin goes active until output is enabled
Hysteresis
Property Name	HYSTWD
Data Type	NUMBER
Description	Hysteretic-window width centered around TH (Threshold voltage)

Property Name	IC_DATA_READY
Data Type	STRING
Options	READY, NOT_READY
Description	Initial condition of the data ready output of a device

Property Name	MIN_CLK
Data Type	NUMBER
Description	Minimum valid clock width

Property Name	SAMPLE_DELAY
Data Type	NUMBER
Description	Time required to sample analog input