The "State of Exit" Data File

At the end of a time-domain simulation, SIMPLIS always writes out the state of the system under study to a "State of Exit" file. This data file contains the voltage across each linear capacitor or piecewise-linear capacitor,

1. The current through each linear inductor or piecewise-linear inductor,
2. The state of each simple switch or simple transistor switch,
3. The segment of operation of each piecewise-linear resistor, and
4. The output logic state of each simple logic gate

where "XXXX" is the name of the input file to SIMPLIS. The "State of Exit" file has been given the file extension ".init" because it is written in a format such that it can be easily merged into the input file to provide initial condition(s) for a continued simulation.

Suppose a simulation has been carried out for 200 microseconds and after examining the data you have decided to run for another 200 microseconds. One approach is to repeat the first simulation with the original initial conditions by changing the run time to 400 microseconds. This approach has the disadvantage of repeating the simulation of the first 200 microseconds. On the other hand, if you are not particularly interested in the waveforms of the first 200 microseconds, the ".init" file can be used to override the initialization provided in the input file by including the contents of this data file in the input file. In such a case, the run time of the second simulation only has to be carried out for 200 microseconds as the ".init" file already contains the state of the system at the end of the first simulation, which is at t = 200 microseconds.