SIMPLIS Parts

Up/Down Counter

The Up/Down Counter models a generic up or down counter with between 2 and 32 output bits. The direction of the counter is based on the CNT_UP pin.

For a counter which counts up, see the Up Counter. For a counter that counts down, see Down Counter.

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Model Name:

Up/Down Counter

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector
Menu Location:

Digital Functions | Counters

Symbol Library:

None - the symbol is automatically generated when placed or edited.

Model File:

None - the device model is generated before simulation.

Subcircuit Name:
  • SIMPLIS_DIGI1_D_UPDOWN_COUNTER_N: Without Ground Reference
  • SIMPLIS_DIGI1_D_UPDOWN_COUNTER_Y: With Ground Reference

Symbols:

Multiple Selections:

Only one device at a time can be edited.

Editing the Up/Down Counter

To configure the up/down counter, follow these steps:

  1. Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Label Parameter Description

Clock to Output Delay

Delay from the triggering clock event until the outputs change

Number of Bits

Number of output bits for the counter

Trigger Condition

Determines the triggering condition of the counter clock pin:

  • 0_TO_1 for rising edge triggered
  • 1_TO_0 for falling edge triggered

Ground Ref

Determines whether or not a device has a ground reference pin.

Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually ground on the schematic. For more information on the use of Ground Ref for digital components, see When is Ground Ref Required?

Minimum Clock Width

Minimum valid clock width. Clock widths less than this parameter will not trigger the counter.

Enable Delay

Delay from when the enable pin goes active until the clock is enabled and the counter starts counting

Setup Time

Minimum time before the triggering clock event that the input signalss must remain steady so that a valid change in each input state is recognized.

Hold Time

Minimum time after the triggering clock event that the input signalss must remain steady so that a valid change in each input state is recognized.

Initial Condition

Initial condition of the counter output in decimal

Set/Reset Delay

Delay from when the SET and RST pin goes active until the counter output is reset

Asynchronous Set/Reset Parameters

Set To

Determines the value of the counter output when the SET pin goes active. To set to the maximum count value, assign a value of -1.

Reset To

Determines the value of the counter output when the RST pin goes active. To reset to 0, assign a assign value of -1 or 0.

Set/Reset Level

Determines the Set/Reset level of counter SET and RST input pin:

  • 1 means active high
  • 0 means active low

Set/Reset Type

Determines whether or not output events are synchronized with a clock event:

Set/Reset Type Set/Reset Behavior
SYNC Set/Reset events are synchronized to the clock edge defined by the Trigger Condition parameter.
ASYNC Set/Reset events are asynchronous to the clock edge.
 

To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps from the Edit Analog-to-Digital Converter dialog box:

  1. Click on the   Interface   tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Label Parameter Description

Input Resistance

Input resistance of each input pin

Threshold

Hysteresis

The Threshold (T) and Hysteresis (H) of the Schmitt trigger input buffer on each Counter input. To determine the low-to-high threshold (TH) and the high-to-low threshold (TL), substitute Threshold (T) and Hysteresis (H) in each of the following formulas :
Input Logic Transition Actual Threshold
0 ➞ 1 TH = Threshold + 0.5 * Hysteresis
1 ➞ 0 TL = Threshold - 0.5 * Hysteresis
 

Output Resistance

Output resistance of the counter output pins

Output High Voltage

Output high voltage for the counter output pins

Output Low Voltage

Output low voltage for the counter output pins

Truth Table

The following truth table assumes a Trigger Condition=0_TO_1 which represents a rising edge clocked Counter.

Inputs

Outputs

Action

EN

SET

RST

CNT_UP

CLK

D0..Dn

1

0

0

0

Count - 1

Count down

1

0

0

1

Count + 1

Count up

0

0

0

0

0 or 1

Last count

Retain last count

0 or 1

1

0

0 or 1

0 or 1

Set To parameter value

Set the counter to the Set To parameter value

0 or 1

0

1

0 or 1

0 or 1

Reset To parameter value

Set the counter to the Reset To parameter value

Examples

The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_030_updowncounter_example.sxsch.

Waveforms

Subcircuit Parameters

Because this up/down-counter model is generated by a template script when the simulation is executed, a fixed model cannot be inserted into a netlist. The template script for this device is simplis_make_counter_model.sxscr, which you, as a licensed user, can download in a zip archive of all built-in scripts.

To download this zip file, follow these steps:

Note: You will be prompted to log in with the user name and password given to you when you registered.

  1. Click here to go to the product-installation page on the SIMetrix website.
  2. Click Download Links in the first paragraph of the product-installation web page.
  3. Scroll down to the Built-in Scripts section.
  4. Right click on Download and select Save target as..., and then navigate to a location on your computer to save the zip file.