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SIMPLIS Parts
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The Unit Delay models a single clock cycle delay in the z-domain. The transfer function in the z-domain from the input I(z) to the output O(z) for the Unit Delay is shown below:
The difference equation representing this transfer function is
As with the other devices in the Discrete Time Filter category, the unit delay is compatible with the SIMPLIS POP and AC Analyses.
Related topics:
In this Topic Hide
Model Name: |
Unit Delay |
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Simulator: |
This device is compatible with the SIMPLIS simulator. |
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Parts Selector |
Digital Functions | Discrete Time Filters |
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Symbol Library: |
None - the symbol is automatically generated when placed or edited. |
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Model File: |
None - the device model is generated before simulation. |
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Subcircuit Name: |
SIMPLIS_DIGI1_D_DF_UNIT_DELAY_Y |
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Symbols: |
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Multiple Selections: |
Only one device at a time can be edited. |
To configure the unit delay, follow these steps:
Label | Parameter Description |
Acquisition Time |
Filter acquisition time in seconds |
Initial Condition |
Initial condition of the filter output |
The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_037_unitdelay_example.sxsch.
In the circuit example, a 100kHz sine wave with a 1V amplitude (+/- 1V peak) is applied to the input of the unit delay. The clock has a frequency of 1MHz, and the sampled input voltage is output on the same graph as the input voltage.
The following AC waveforms confirm that the DC gain is 0dB and that the phase change at 1/2 the sampling frequency is the expected 270 degrees.
Because this unit delay model is generated by a template script when the simulation is executed, a fixed model cannot be inserted into a netlist. The template script for this device is simplis_make_digital_filter_model.sxscr, which you, as a licensed user, can download in a zip archive of all built-in scripts.
To download this zip file, follow these steps:
Note: You will be prompted to log in with the user name and password given to you when you registered.