SIMPLIS Parts

J/K Flip-Flop with Set/Reset

The J/K Flip-Flop with Set/Reset models a generic clocked J/K Flip-Flop with either asynchronous or synchronous set and reset inputs. The Q and QN outputs can change state only on the specified clock edge unless the asynchronous set or reset is asserted. The clock edge trigger can be set with the Trigger Condition parameter to be either rising edge ( 0_TO_1 ) or falling edge ( 1_TO_0 ). If set and reset inputs are not required, the J/K Flip-Flop the J/K Flip-Flop can be used.

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Model Name:

J/K Flip-Flop with Set/Reset

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector
Menu Location:

Digital Functions | Flip-Flops

Symbol Library:

None - the symbol is automatically generated when placed or edited.

Model File:

SIMPLIS_DIGI1.lb

Subcircuit Name:

  • SIMPLIS_DIGI1_JKFF_SR_N: Without Ground Reference
  • SIMPLIS_DIGI1_JKFF_SR_Y: With Ground Reference

Symbols:


 

Multiple Selections:

Only one device at a time can be edited.

Editing the J/K Flip-Flop with Set/Reset

To configure the J/K Flip-Flop with set/reset, follow these steps:

  1. Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Label Parameter Description

Clock to Output Delay

Delay from the triggering clock event until the outputs change

Minimum Clock Width

Minimum valid clock width. Clock widths less than this parameter will not trigger the Flip-Flop.

Trigger Condition

Determines the triggering condition of the clock pin:

  • 0_TO_1 for rising edge triggered
  • 1_TO_0 for falling edge triggered

Initial Condition

Initial condition of the Q output at time=0

Setup Time

Minimum time before the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized.

Hold Time

Minimum time after the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized.

Ground Ref

Determines whether or not a device has a ground reference pin.

Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic. Click on the Help button for more information.

Set/Reset Delay

Delay from when the SET or RST pin goes active until the Q output is actually set or reset

Set/Reset Level

Determines the Set/Reset level of a device:

  • 1 means active high
  • 0 means active low

Set/Reset Type

Determines whether or not output events are synchronized with a clock event:

Set/Reset TypeSet/Reset Behavior
SYNCSet/Reset events are synchronized to the clock edge defined by the Trigger Condition parameter.
ASYNCSet/Reset events are asynchronous to the clock edge.
 
p>To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps from the Edit J/K Flip-Flop with Set/Reset dialog box:

  1. Click on the   Interface   tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Label Parameter Description

Input Resistance

Input resistance of each input pin

Threshold

Hysteresis

The Threshold (T) and Hysteresis (H) of the Schmitt trigger input buffer on each Flip-Flop input. To determine the low-to-high threshold (TH) and the high-to-low threshold (TL), substitute Threshold (T) and Hysteresis (H) in each of the following formulas :
Input Logic Transition Actual Threshold
0 ➞ 1 TH = Threshold + 0.5 * Hysteresis
1 ➞ 0 TL = Threshold - 0.5 * Hysteresis
 

Output Resistance

Output resistance of Q and QN pins

Output High Voltage

Output high voltage for Q and QN pins

Output Low Voltage

Output low voltage for Q and QN pins

Truth Table

The following truth table assumes a Trigger Condition=0_TO_1 which represents a rising edge clocked Flop-Flop, Set/Reset level=1, and Set/Reset Type=ASYNC, representing asynchronous set/reset.

Inputs

Outputs

Action

J

K

CLK

SET

RST

Q

QN

0

0

0

0

Last Q

Last QN

Retain State

0

1

0

0

0

1

Reset the Flip-Flop

1

0

0

0

1

0

Set the Flip-Flop

1

1

0

0

Last QN

Last Q

Toggle the Flip-Flop

0 or 1

0 or 1

0 or 1

1

0

1

0

Asynchronously set the Flip-Flop

0 or 1

0 or 1

0 or 1

0

1

0

1

Asynchronously reset the Flip-Flop

0 or 1

0 or 1

0 or 1

1

1

Last Q

Last QN

Illegal concurrent SET and RST

The following truth table assumes a Trigger Condition=0_TO_1 which represents a rising edge clocked Flop-Flop, Set/Reset level=1, and Set/Reset Type=SYNC, representing synchronous set/reset.

Inputs

Outputs

Action

J

K

CLK

SET

RST

Q

QN

0

0

0

0

Last Q

Last QN

Retain State

0

1

0

0

0

1

Reset the Flip-Flop

1

0

0

0

1

0

Set the Flip-Flop

1

1

0

0

Last QN

Last Q

Toggle the Flip-Flop

0 or 1

0 or 1

1

0

1

0

Synchronously set the Flip-Flop

0 or 1

0 or 1

0

1

0

1

Synchronously reset the Flip-Flop

0 or 1

0 or 1

1

1

Last Q

Last QN

Illegal concurrent SET and RST

Examples

The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_016_jkflipflopwsetrst_example.sxsch.

Waveforms

The following waveforms assume Trigger Condition=0_TO_1 which represents a rising edge clocked Flop-Flop, Set/Reset level=1, and Set/Reset Type=ASYNC, representing asynchronous set/reset.

Subcircuit Parameters

The subcircuit parameters, parameter names, data types, ranges, units, and descriptions are in the following table. The parameter names can be used to directly generate netlist entries for the device. For example, a J/K Flip-Flop with set/reset netlist entry without ground reference would be:
X$U1 4 7 3 6 5 8 9 SIMPLIS_DIGI1_JKFF_SR_N vars: IC=0 MIN_CLK=10p TRIG_COND='0_TO_1' CLK_TO_OUT_DELAY=20p SETUP_TIME=10p HOLD_TIME=1p SET_RESET_DELAY=15p SET_RESET_TYPE='ASYNC' SET_RESET_LEVEL=1 GNDREF='N'


Parameter Name Label Data Type Range Units Parameter Description

CLK_TO_OUT_DELAY

Clock to Output Delay

  

1f to 1024

s

Delay from the triggering clock event until the outputs change

HOLD_TIME

Hold Time

  

1f to 1024

s

Minimum time after the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized.

HYSTWD

Hysteresis

    

V

The Threshold (T) and Hysteresis (H) of the Schmitt trigger input buffer on each Flip-Flop input. To determine the low-to-high threshold (TH) and the high-to-low threshold (TL), substitute Threshold (T) and Hysteresis (H) in each of the following formulas :

Input Logic Transition Actual Threshold
0 ➞ 1 TH = Threshold + 0.5 * Hysteresis
1 ➞ 0 TL = Threshold - 0.5 * Hysteresis
 

IC

Initial Condition

LIST

0,
1

  

Initial condition of the Q output at time=0

RIN

Input Resistance

  

min: 100

Ω

Input resistance of each input pin

MIN_CLK

Minimum Clock Width

  

1f to 1024

s

Minimum valid clock width. Clock widths less than this parameter will not trigger the Flip-Flop.

VOH

Output High Voltage

    

V

Output high voltage for Q and QN pins

VOL

Output Low Voltage

    

V

Output low voltage for Q and QN pins

ROUT

Output Resistance

  

min: 1m

Ω

Output resistance of Q and QN pins

SET_RESET_DELAY

Set/Reset Delay

  

1f to 1024

s

Delay from when the SET or RST pin goes active until the Q output is actually set or reset

SET_RESET_LEVEL

Set/Reset Level

LIST

0,
1

  

Determines the Set/Reset level of a device:

  • 1 means active high
  • 0 means active low

SET_RESET_TYPE

Set/Reset Type

LIST

SYNC,
ASYNC

  

Determines whether or not output events are synchronized with a clock event:

Set/Reset TypeSet/Reset Behavior
SYNCSet/Reset events are synchronized to the clock edge defined by the Trigger Condition parameter.
ASYNCSet/Reset events are asynchronous to the clock edge.
 

SETUP_TIME

Setup Time

  

1f to 1024

s

Minimum time before the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized.

TH

Threshold

    

V

The Threshold (T) and Hysteresis (H) of the Schmitt trigger input buffer on each Flip-Flop input. To determine the low-to-high threshold (TH) and the high-to-low threshold (TL), substitute Threshold (T) and Hysteresis (H) in each of the following formulas :

Input Logic Transition Actual Threshold
0 ➞ 1 TH = Threshold + 0.5 * Hysteresis
1 ➞ 0 TL = Threshold - 0.5 * Hysteresis
 

TRIG_COND

Trigger Condition

LIST

0_TO_1,
1_TO_0

  

Determines the triggering condition of the clock pin:

  • 0_TO_1 for rising edge triggered
  • 1_TO_0 for falling edge triggered