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There are three Verilog simulation options available through the user interface. These can be accessed from the Choose Analysis dialog box as follows:
This option allows you to select the Verilog simulator used for the main simulation. There will be a default choice of 'CVER' or 'Icarus'.
Note that the Verilog simulator is also used to enumerate the ports and parameters of a Verilog module separately from the main simulation. This task is always performed by 'GPL Cver' regardless of the simulator setting.
Verilog simulations use 64bit integer values throughout and this includes time. To convert to real time, the value of each time 'tick' needs to be defined. This is the timing resolution defined here.
The default value is 1fs and there is no benefit in changing this unless the simulation runs for longer than $2^{64}$ x 1fs. This is approximately 18000 seconds.
Note that the timescale setting used to define the values of delays etc. within each module, is not affected by this setting.
If you set this check box, a console window will open for the run and any messages generated by the Verilog simulation will be displayed in that window.
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