* SCHEMATIC : ..\..\4.2_LTC3406B - DVM ADVANCED.sxsch
* TESTPLAN : dvm_advanced.testplan
* ORIGINALTP: dvm_builtin-efficiency_dcdc_1in_1out.testplan
* DATE : 2015-12-10
* TIME : 5:43 PM
* REPORT DIR: D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM
* NUM TESTS : 34
* HTMLTITLE : SIMPLIS DVM Test Report Overview
*
*
* TEST : Steady-State|Steady-State|Vin Nominal|Light Load
* PROGRESS : 1 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\Light Load/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\Light Load\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|10%
* PROGRESS : 2 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\10%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\10%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\10%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\10%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|20%
* PROGRESS : 3 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\20%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\20%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\20%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\20%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|30%
* PROGRESS : 4 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\30%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\30%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\30%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\30%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|40%
* PROGRESS : 5 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\40%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\40%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\40%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\40%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|50%
* PROGRESS : 6 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\50%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\50%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\50%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\50%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|60%
* PROGRESS : 7 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\60%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\60%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\60%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\60%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|70%
* PROGRESS : 8 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\70%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\70%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\70%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\70%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|80%
* PROGRESS : 9 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\80%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\80%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\80%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\80%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|90%
* PROGRESS : 10 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\90%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\90%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\90%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\90%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|100%
* PROGRESS : 11 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Nominal\100%/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\100%\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\100%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\100%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|Light Load
* PROGRESS : 12 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\Light Load/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\Light Load\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\Light Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|10%
* PROGRESS : 13 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\10%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\10%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\10%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\10%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|20%
* PROGRESS : 14 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\20%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\20%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\20%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\20%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|30%
* PROGRESS : 15 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\30%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\30%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\30%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\30%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|40%
* PROGRESS : 16 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\40%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\40%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\40%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\40%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|50%
* PROGRESS : 17 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\50%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\50%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\50%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\50%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|60%
* PROGRESS : 18 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\60%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\60%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\60%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\60%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|70%
* PROGRESS : 19 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\70%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\70%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\70%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\70%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|80%
* PROGRESS : 20 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\80%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\80%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\80%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\80%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|90%
* PROGRESS : 21 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\90%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\90%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\90%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\90%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|100%
* PROGRESS : 22 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Maximum\100%/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\100%\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\100%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\100%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|Light Load
* PROGRESS : 23 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\Light Load/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\Light Load\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\Light Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|10%
* PROGRESS : 24 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\10%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\10%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\10%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\10%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|20%
* PROGRESS : 25 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\20%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\20%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\20%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\20%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|30%
* PROGRESS : 26 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\30%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\30%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\30%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\30%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|40%
* PROGRESS : 27 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\40%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\40%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\40%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\40%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|50%
* PROGRESS : 28 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\50%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\50%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\50%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\50%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|60%
* PROGRESS : 29 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\60%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\60%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\60%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\60%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|70%
* PROGRESS : 30 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\70%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\70%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\70%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\70%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|80%
* PROGRESS : 31 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\80%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\80%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\80%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\80%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|90%
* PROGRESS : 32 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\90%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\90%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\90%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\90%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|100%
* PROGRESS : 33 of 34
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Steady-State\Vin Minimum\100%/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\100%\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\100%\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\100%\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Generate Efficiency Curves
* PROGRESS : 34 of 34
* SIMULATOR : simplis
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_43_PM\Steady-State\Generate Efficiency Curves/report.txt
* SIMULATOR : N/A
* STATUS : SKIP
* FEATURE : 34|DVM Efficiency
* RSTATUS : SKIP
* REPORT : Steady-State\Generate Efficiency Curves\report.txt.html
* TEST TIME : 3 seconds
*
*
* TOTAL TIME: 289 seconds
* TESTS RUN : 34 of 34