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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|70% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Minimum|70% Load
Date / Time 12/10/2015 6:16 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\70% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.4761%
eta_min 95.4761%
Frequency(CLK) 78.8499k
gain_crossover_freq 4.63969k
gain_margin 19.6913
gmargin_min 19.6913
gxover_min 4.63969k
ILOAD
AVG
3.51122
MIN
3.50608
MAX
3.515
RMS
3.51122
PK2PK
8.91618m
iload_min 3.51122
ISRC
AVG
245.988m
MIN
-558.657m
MAX
944.961m
RMS
468.026m
PK2PK
1.50362
min_phase 49.0723
min_phase_freq 4.63969k
phase_crossover_freq 17.6783k
phase_margin 49.0675
pmargin_min 49.0675
Power(LOAD) 84.5286
Power(SRC) 88.5337
sw_freq_min 78.8499k
VLOAD
AVG
24.0739
MIN
24.0388
MAX
24.0997
RMS
24.0739
PK2PK
60.8942m
VSRC
AVG
359.975
MIN
359.906
MAX
360.056
RMS
359.975
PK2PK
150.362m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.0997) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0388) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (19.6913) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (49.0675) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac39_2334.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop39_2300.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop39_2290.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop39_2281.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop39_2295.sxgph
Other SXGPH Files
default#2323#pop simplis_pop39_2323.sxgph
Modulator#pop simplis_pop39_2328.sxgph