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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|90% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Minimum|90% Load
Date / Time 12/10/2015 6:16 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\90% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.1984%
eta_min 95.1984%
Frequency(CLK) 78.4924k
gain_crossover_freq 4.45169k
gain_margin 17.151
gmargin_min 17.151
gxover_min 4.45169k
ILOAD
AVG
4.50931
MIN
4.50083
MAX
4.51548
RMS
4.50931
PK2PK
14.648m
iload_min 4.50931
ISRC
AVG
316.493m
MIN
-550.195m
MAX
1.14515
RMS
561.564m
PK2PK
1.69534
min_phase 52.0485
min_phase_freq 4.45169k
phase_crossover_freq 14.5165k
phase_margin 51.673
pmargin_min 51.673
Power(LOAD) 108.437
Power(SRC) 113.906
sw_freq_min 78.4924k
VLOAD
AVG
24.0473
MIN
24.0022
MAX
24.0801
RMS
24.0473
PK2PK
77.9075m
VSRC
AVG
359.968
MIN
359.885
MAX
360.055
RMS
359.968
PK2PK
169.534m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.0801) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0022) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (17.151) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (51.673) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac41_2454.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop41_2420.sxgph
SRC
ISRC
VSRC
SXGPH File simplis_pop41_2410.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop41_2401.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop41_2415.sxgph
Other SXGPH Files
default#2443#pop simplis_pop41_2443.sxgph
Modulator#pop simplis_pop41_2448.sxgph