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» DVM Test Report: Steady-State|Steady-State|Vin Minimum|20%

Test Details
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Steady-State|Vin Minimum|20%
Date / Time 12/10/2015 5:46 PM
Report Directory run_blt_in_and_prmt_grphs\Steady-State\Steady-State\VinMinimum\20%
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 88.6078%
Efficiency_Min 88.6078%
Frequency(CLK) 955.66k
ILOAD
AVG
300.125m
MIN
299.419m
MAX
300.717m
RMS
300.126m
PK2PK
1.29866m
ISRC
AVG
113.336m
MIN
380.948u
MAX
551.976m
RMS
205.616m
PK2PK
551.595m
Power(LOAD) 451.874m
Power(SRC) 509.971m
VLOAD
AVG
1.50562
MIN
1.50207
MAX
1.50859
RMS
1.50562
PK2PK
6.51487m
VSRC
AVG
4.49989
MIN
4.49945
MAX
4.5
RMS
4.49989
PK2PK
551.595u
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.50859) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.50207) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop25_859.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop25_849.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop25_854.sxgph
Other SXGPH Files
clock#pop simplis_pop25_841.sxgph